| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 1082 const MCOperand &RegOp = Inst.getOperand(0); in expandLoadImm() local
1083 assert(RegOp.isReg() && "expected register operand kind"); in expandLoadImm()
1093 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg())); in expandLoadImm()
1101 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg())); in expandLoadImm()
1111 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg())); in expandLoadImm()
1114 createShiftOr<0, false>(ImmValue, RegOp.getReg(), IDLoc, Instructions); in expandLoadImm()
1136 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg())); in expandLoadImm()
1140 createShiftOr<16, false>(ImmValue, RegOp.getReg(), IDLoc, Instructions); in expandLoadImm()
1141 createShiftOr<0, true>(ImmValue, RegOp.getReg(), IDLoc, Instructions); in expandLoadImm()
1163 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg())); in expandLoadImm()
[all …]
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| /external/llvm/lib/Target/Mips/ |
| D | MipsAsmPrinter.cpp | 503 unsigned RegOp = OpNum; in PrintAsmOperand() local
509 RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum; in PrintAsmOperand()
512 RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1; in PrintAsmOperand()
515 RegOp = OpNum + 1; in PrintAsmOperand()
517 if (RegOp >= MI->getNumOperands()) in PrintAsmOperand()
519 const MachineOperand &MO = MI->getOperand(RegOp); in PrintAsmOperand()
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| /external/llvm/lib/Target/X86/AsmParser/ |
| D | X86Operand.h | 41 struct RegOp { struct
60 struct RegOp Reg;
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.cpp | 93 uint16_t RegOp; member
275 unsigned RegOp = OpTbl2Addr[i].RegOp; in X86InstrInfo() local
279 RegOp, MemOp, in X86InstrInfo()
384 unsigned RegOp = OpTbl0[i].RegOp; in X86InstrInfo() local
388 RegOp, MemOp, TB_INDEX_0 | Flags); in X86InstrInfo()
619 unsigned RegOp = OpTbl1[i].RegOp; in X86InstrInfo() local
623 RegOp, MemOp, in X86InstrInfo()
1274 unsigned RegOp = OpTbl2[i].RegOp; in X86InstrInfo() local
1278 RegOp, MemOp, in X86InstrInfo()
1436 unsigned RegOp = OpTbl3[i].RegOp; in X86InstrInfo() local
[all …]
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| D | X86MCInstLower.cpp | 298 unsigned RegOp = IsStore ? 0 : 5; in SimplifyShortMoveForm() local
300 assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() && in SimplifyShortMoveForm()
310 unsigned Reg = Inst.getOperand(RegOp).getReg(); in SimplifyShortMoveForm()
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| D | X86InstrInfo.h | 164 unsigned RegOp, unsigned MemOp, unsigned Flags);
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| /external/llvm/lib/Target/SystemZ/AsmParser/ |
| D | SystemZAsmParser.cpp | 81 struct RegOp { struct in __anon93072fb70111::SystemZOperand
101 RegOp Reg;
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| /external/llvm/lib/Target/Sparc/AsmParser/ |
| D | SparcAsmParser.cpp | 157 struct RegOp { struct in __anon6d25192b0111::SparcOperand
174 struct RegOp Reg;
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| /external/llvm/lib/CodeGen/AsmPrinter/ |
| D | DwarfUnit.cpp | 1821 const MachineOperand RegOp = DVInsn->getOperand(0); in constructVariableDIEImpl() local
1824 MachineLocation Location(RegOp.getReg(), in constructVariableDIEImpl()
1827 } else if (RegOp.getReg()) in constructVariableDIEImpl()
1828 addVariableAddress(DV, *VariableDie, MachineLocation(RegOp.getReg())); in constructVariableDIEImpl()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMAsmPrinter.cpp | 328 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1; in PrintAsmOperand() local
329 if (RegOp >= MI->getNumOperands()) in PrintAsmOperand()
331 const MachineOperand &MO = MI->getOperand(RegOp); in PrintAsmOperand()
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 172 struct RegOp { struct in __anon27fec24b0211::AArch64Operand
237 struct RegOp Reg;
3785 AArch64Operand &RegOp = static_cast<AArch64Operand &>(*Operands[1]); in MatchAndEmitInstruction() local
3787 if (RegOp.isReg() && ImmOp.isFPImm() && ImmOp.getFPImm() == (unsigned)-1) { in MatchAndEmitInstruction()
3790 RegOp.getReg()) in MatchAndEmitInstruction()
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 443 struct RegOp { struct in __anon92bc5ab90311::ARMOperand
521 struct RegOp Reg;
4390 unsigned RegOp = 4; in cvtThumbMultiply() local
4394 RegOp = 5; in cvtThumbMultiply()
4395 ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1); in cvtThumbMultiply()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfoV4.td | 1019 bits<5> RegOp; // Non-New-Value Operand
1027 let RegOp = !if(!eq(NvOpNum, 0), src2, src1);
1035 let Inst{12-8} = RegOp;
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