| /external/llvm/lib/Target/Mips/ |
| D | MipsSEFrameLowering.cpp | 61 void expandLoadACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize);
63 unsigned MFLoOpc, unsigned RegSize);
164 unsigned RegSize) { in expandLoadACC() argument
177 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandLoadACC()
188 TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize); in expandLoadACC()
194 unsigned RegSize) { in expandStoreACC() argument
207 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandStoreACC()
217 TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize); in expandStoreACC()
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| D | MipsISelLowering.cpp | 3449 unsigned RegSize = regSize(); in handleByValArg() local
3450 unsigned ByValSize = RoundUpToAlignment(ArgFlags.getByValSize(), RegSize); in handleByValArg()
3451 unsigned Align = std::min(std::max(ArgFlags.getByValAlign(), RegSize), in handleByValArg()
3452 RegSize * 2); in handleByValArg()
3458 ByVal.Address = CCInfo.AllocateStack(ByValSize - RegSize * ByVal.NumRegs, in handleByValArg()
3497 unsigned RegSize = regSize(), NumIntArgRegs = numIntArgRegs(); in allocateRegs() local
3499 assert(!(ByValSize % RegSize) && !(Align % RegSize) && in allocateRegs()
3506 if ((Align > RegSize) && (ByVal.FirstIdx % 2)) { in allocateRegs()
3513 ByValSize -= RegSize, ++I, ++ByVal.NumRegs) in allocateRegs()
3679 unsigned RegSize = CC.regSize(); in writeVarArgRegs() local
[all …]
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| /external/llvm/lib/CodeGen/AsmPrinter/ |
| D | AsmPrinterDwarf.cpp | 294 unsigned RegSize = TRI->getMinimalPhysRegClass(MLoc.getReg())->getSize() * 8; in EmitDwarfRegOpPiece() local
297 SmallBitVector Coverage(RegSize, false); in EmitDwarfRegOpPiece()
306 SmallBitVector Intersection(RegSize, false); in EmitDwarfRegOpPiece()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrInfo.cpp | 632 LogicOp() : RegSize(0), ImmLSB(0), ImmSize(0) {} in LogicOp()
634 : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {} in LogicOp()
636 operator bool() const { return RegSize; } in operator bool()
638 unsigned RegSize, ImmLSB, ImmSize; member
722 Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB); in convertToThreeAddress()
724 if (isRxSBGMask(Imm, And.RegSize, Start, End)) { in convertToThreeAddress()
726 if (And.RegSize == 64) in convertToThreeAddress()
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| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 41 const uint16_t RegSize, Alignment; // Size & Alignment of register in bytes variable
86 unsigned getSize() const { return RegSize; } in getSize()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64LoadStoreOptimizer.cpp | 704 unsigned RegSize = TII->getRegClass(MemMI->getDesc(), 0, TRI, MF)->getSize(); in findMatchingUpdateInsnBackward() local
732 if (isMatchingUpdateInsn(MI, BaseReg, RegSize)) in findMatchingUpdateInsnBackward()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.cpp | 709 unsigned RegSize = RegisterVT.getSizeInBits(); in getCopyFromRegs() local
713 if (NumZeroBits == RegSize) { in getCopyFromRegs()
725 if (NumSignBits == RegSize) in getCopyFromRegs()
727 else if (NumZeroBits >= RegSize-1) in getCopyFromRegs()
729 else if (NumSignBits > RegSize-8) in getCopyFromRegs()
731 else if (NumZeroBits >= RegSize-8) in getCopyFromRegs()
733 else if (NumSignBits > RegSize-16) in getCopyFromRegs()
735 else if (NumZeroBits >= RegSize-16) in getCopyFromRegs()
737 else if (NumSignBits > RegSize-32) in getCopyFromRegs()
739 else if (NumZeroBits >= RegSize-32) in getCopyFromRegs()
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| /external/clang/lib/CodeGen/ |
| D | TargetInfo.cpp | 3551 int RegSize; in EmitAArch64VAArg() local
3558 RegSize = 8 * AllocatedGPR; in EmitAArch64VAArg()
3565 RegSize = 16 * AllocatedVFP; in EmitAArch64VAArg()
3603 reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, RegSize), "new_reg_offs"); in EmitAArch64VAArg()
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