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Searched refs:SETEQ (Results 1 – 25 of 41) sorted by relevance

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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
DAMDGPUISelLowering.cpp208 ISD::SETEQ); in LowerUDIVREM()
222 ISD::SETEQ); in LowerUDIVREM()
259 Quotient, Quotient_A_One, ISD::SETEQ); in LowerUDIVREM()
263 Quotient_S_One, Div, ISD::SETEQ); in LowerUDIVREM()
275 Remainder, Remainder_S_Den, ISD::SETEQ); in LowerUDIVREM()
279 Remainder_A_Den, Rem, ISD::SETEQ); in LowerUDIVREM()
DAMDGPUInstructions.td40 case ISD::SETEQ: return true;}}}]
DR600ISelLowering.cpp450 case ISD::SETEQ: in LowerSELECT_CC()
DSIInstructions.td85 [(set SCCReg:$dst, (setcc SReg_32:$src0, imm:$src1, SETEQ))]
254 [(set VCCReg:$dst, (setcc (i32 AllReg_32:$src0), VReg_32:$src1, SETEQ))]
/external/mesa3d/src/gallium/drivers/radeon/
DAMDGPUISelLowering.cpp208 ISD::SETEQ); in LowerUDIVREM()
222 ISD::SETEQ); in LowerUDIVREM()
259 Quotient, Quotient_A_One, ISD::SETEQ); in LowerUDIVREM()
263 Quotient_S_One, Div, ISD::SETEQ); in LowerUDIVREM()
275 Remainder, Remainder_S_Den, ISD::SETEQ); in LowerUDIVREM()
279 Remainder_A_Den, Rem, ISD::SETEQ); in LowerUDIVREM()
DAMDGPUInstructions.td40 case ISD::SETEQ: return true;}}}]
DR600ISelLowering.cpp450 case ISD::SETEQ: in LowerSELECT_CC()
/external/llvm/lib/Target/Hexagon/
DHexagonSelectCCInfo.td15 IntRegs:$fval, SETEQ)),
77 // Convert Rd = selectcc(p0, p1, true_val, false_val, SETEQ) into:
88 IntRegs:$fval, SETEQ)),
/external/llvm/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp127 case ISD::SETEQ: in softenSetCCOperands()
1244 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && in SimplifySetCC()
1246 if ((C1 == 0) == (Cond == ISD::SETEQ)) { in SimplifySetCC()
1253 Cond = ISD::SETEQ; in SimplifySetCC()
1278 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; in SimplifySetCC()
1287 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { in SimplifySetCC()
1392 case ISD::SETEQ: return DAG.getConstant(0, VT); in SimplifySetCC()
1411 case ISD::SETEQ: in SimplifySetCC()
1434 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { in SimplifySetCC()
1464 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { in SimplifySetCC()
[all …]
DLegalizeIntegerTypes.cpp865 case ISD::SETEQ: in PromoteSetCCOperands()
1185 N->getOperand(2), ISD::SETEQ); in ExpandIntegerResult()
2035 ISD::SETEQ : ISD::SETNE); in ExpandIntRes_SADDSUBO()
2294 RHS, DAG.getConstant(0, VT), ISD::SETEQ); in ExpandIntRes_XMULO()
2523 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) { in IntegerExpandSetCCOperands()
2610 LHSHi, RHSHi, ISD::SETEQ, false, in IntegerExpandSetCCOperands()
2614 LHSHi, RHSHi, ISD::SETEQ); in IntegerExpandSetCCOperands()
DSelectionDAGDumper.cpp314 case ISD::SETEQ: return "seteq"; in getOperationName()
DSelectionDAGBuilder.cpp1403 Condition = ISD::SETEQ; // silence warning. in EmitBranchForMergedCondition()
1415 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()), in EmitBranchForMergedCondition()
1547 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB) in ShouldEmitAsBranches()
1639 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()), in visitBr()
1660 CB.CC == ISD::SETEQ) in visitSwitchCase()
1663 CB.CC == ISD::SETEQ) { in visitSwitchCase()
1947 ISD::SETEQ); in visitBitTestCase()
2118 ISD::SETEQ); in handleSmallSwitchRange()
2191 CC = ISD::SETEQ; in handleSmallSwitchRange()
DLegalizeDAG.cpp1723 case ISD::SETEQ: in LegalizeSetCCCondCode()
1725 InvCC = CCCode == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ; in LegalizeSetCCCondCode()
3071 Res, Node->getOperand(2), ISD::SETEQ); in ExpandNode()
3758 ISD::SETEQ : ISD::SETNE); in ExpandNode()
4163 ISD::SETEQ); in PromoteNode()
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h783 SETEQ, // 1 X 0 0 1 True if equal enumerator
/external/llvm/lib/CodeGen/
DTargetLoweringBase.cpp642 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; in InitCmpLibcallCCs()
643 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; in InitCmpLibcallCCs()
644 CCs[RTLIB::OEQ_F128] = ISD::SETEQ; in InitCmpLibcallCCs()
663 CCs[RTLIB::O_F32] = ISD::SETEQ; in InitCmpLibcallCCs()
664 CCs[RTLIB::O_F64] = ISD::SETEQ; in InitCmpLibcallCCs()
665 CCs[RTLIB::O_F128] = ISD::SETEQ; in InitCmpLibcallCCs()
DAnalysis.cpp175 case ISD::SETOEQ: case ISD::SETUEQ: return ISD::SETEQ; in getFCmpCodeWithoutNaN()
190 case ICmpInst::ICMP_EQ: return ISD::SETEQ; in getICmpCondCode()
/external/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp499 if (CC == ISD::SETEQ || CC == ISD::SETNE) { in SelectCC()
540 if (CC == ISD::SETEQ || CC == ISD::SETNE) { in SelectCC()
599 case ISD::SETEQ: return PPC::PRED_EQ; in getPredicateForSetCC()
630 case ISD::SETEQ: return 2; // Bit #2 = SETOEQ in getCRIdxForSetCC()
656 case ISD::SETEQ: in getVCmpInst()
760 case ISD::SETEQ: { in SelectSETCC()
789 case ISD::SETEQ: in SelectSETCC()
836 case ISD::SETEQ: in SelectSETCC()
DPPCInstrInfo.td2504 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)),
2577 defm : ExtSetCCPat<SETEQ,
2666 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)),
2668 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)),
2682 def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)),
2711 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)),
2734 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)),
2736 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)),
2750 def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)),
2779 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)),
[all …]
DPPCISelLowering.cpp1728 if (CC == ISD::SETEQ || CC == ISD::SETNE) { in LowerSETCC()
1747 if (C->isNullValue() && CC == ISD::SETEQ) { in LowerSETCC()
1773 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) { in LowerSETCC()
5007 case ISD::SETEQ: in LowerSELECT_CC()
5039 case ISD::SETEQ: in LowerSELECT_CC()
8013 N->getOperand(0), Zero, ISD::SETEQ); in PerformDAGCombine()
8412 assert((CC == ISD::SETEQ || CC == ISD::SETNE) && in PerformDAGCombine()
8416 bool isBDNZ = (CC == ISD::SETEQ && Val) || in PerformDAGCombine()
8433 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) && in PerformDAGCombine()
8441 if (CC == ISD::SETEQ) // Cond never true, remove branch. in PerformDAGCombine()
[all …]
/external/llvm/lib/Target/R600/
DAMDGPUInstructions.td63 [{return N->get() == ISD::SETOEQ || N->get() == ISD::SETEQ;}]
118 [{return N->get() == ISD::SETEQ || N->get() == ISD::SETUEQ;}]
DAMDGPUISelLowering.cpp971 case ISD::SETEQ: in CombineMinMax()
1549 ISD::SETEQ); in LowerUDIVREM()
1563 ISD::SETEQ); in LowerUDIVREM()
1600 Quotient, Quotient_A_One, ISD::SETEQ); in LowerUDIVREM()
1604 Quotient_S_One, Div, ISD::SETEQ); in LowerUDIVREM()
1616 Remainder, Remainder_S_Den, ISD::SETEQ); in LowerUDIVREM()
1620 Remainder_A_Den, Rem, ISD::SETEQ); in LowerUDIVREM()
DR600ISelLowering.cpp910 SDValue REM_Lo = DAG.getSelectCC(DL, RHS_Hi, zero, REM_Part, LHS_Hi, ISD::SETEQ); in ReplaceNodeResults()
912 SDValue DIV_Hi = DAG.getSelectCC(DL, RHS_Hi, zero, DIV_Part, zero, ISD::SETEQ); in ReplaceNodeResults()
1980 case ISD::SETEQ: { in PerformDAGCombine()
/external/llvm/lib/Target/Mips/
DMipsDSPInstrInfo.td1360 def : DSPSetCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;
1366 def : DSPSetCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;
1373 def : DSPSelectCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;
1379 def : DSPSelectCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp207 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ); in ARMTargetLowering()
226 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ); in ARMTargetLowering()
275 { RTLIB::UNE_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ }, in ARMTargetLowering()
281 { RTLIB::O_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ }, in ARMTargetLowering()
293 { RTLIB::UNE_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ }, in ARMTargetLowering()
299 { RTLIB::O_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ }, in ARMTargetLowering()
1143 case ISD::SETEQ: return ARMCC::EQ; in IntCCToARMCC()
1161 case ISD::SETEQ: in FPCCToARMCC()
3369 return ISD::SETEQ; in getInverseCCForVSEL()
3594 CC = ISD::SETEQ; in OptimizeVFPBrcond()
[all …]
/external/llvm/include/llvm/Target/
DTargetSelectionDAG.td510 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
869 (setcc node:$lhs, node:$rhs, SETEQ)>;

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