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Searched refs:SETLT (Results 1 – 25 of 36) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h786 SETLT, // 1 X 1 0 0 True if less than enumerator
797 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE; in isSignedIntSetCC()
/external/llvm/lib/Target/Hexagon/
DHexagonSelectCCInfo.td43 IntRegs:$fval, SETLT)),
113 DoubleRegs:$fval, SETLT)),
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
DAMDILISelLowering.cpp601 ISD::SETLT); in LowerSDIV32()
608 ISD::SETLT); in LowerSDIV32()
707 SDValue r10 = DAG.getSetCC(DL, OVT, r0, DAG.getConstant(0, OVT), ISD::SETLT); in LowerSREM32()
710 SDValue r11 = DAG.getSetCC(DL, OVT, r1, DAG.getConstant(0, OVT), ISD::SETLT); in LowerSREM32()
DAMDGPUInstructions.td67 case ISD::SETLT: return true;}}}]
DR600Instructions.td1193 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETLT),
/external/mesa3d/src/gallium/drivers/radeon/
DAMDILISelLowering.cpp601 ISD::SETLT); in LowerSDIV32()
608 ISD::SETLT); in LowerSDIV32()
707 SDValue r10 = DAG.getSetCC(DL, OVT, r0, DAG.getConstant(0, OVT), ISD::SETLT); in LowerSREM32()
710 SDValue r11 = DAG.getSetCC(DL, OVT, r1, DAG.getConstant(0, OVT), ISD::SETLT); in LowerSREM32()
DAMDGPUInstructions.td67 case ISD::SETLT: return true;}}}]
/external/llvm/lib/CodeGen/
DAnalysis.cpp177 case ISD::SETOLT: case ISD::SETULT: return ISD::SETLT; in getFCmpCodeWithoutNaN()
196 case ICmpInst::ICMP_SLT: return ISD::SETLT; in getICmpCondCode()
DTargetLoweringBase.cpp651 CCs[RTLIB::OLT_F32] = ISD::SETLT; in InitCmpLibcallCCs()
652 CCs[RTLIB::OLT_F64] = ISD::SETLT; in InitCmpLibcallCCs()
653 CCs[RTLIB::OLT_F128] = ISD::SETLT; in InitCmpLibcallCCs()
/external/llvm/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp142 case ISD::SETLT: in softenSetCCOperands()
1400 case ISD::SETLT: in SimplifySetCC()
1579 ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT; in SimplifySetCC()
1590 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) in SimplifySetCC()
1603 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) in SimplifySetCC()
1607 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) in SimplifySetCC()
1625 ISD::SETLT); in SimplifySetCC()
1970 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X in SimplifySetCC()
DSelectionDAGDumper.cpp317 case ISD::SETLT: return "setlt"; in getOperationName()
DLegalizeIntegerTypes.cpp879 case ISD::SETLT: in PromoteSetCCOperands()
2546 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0 in IntegerExpandSetCCOperands()
2557 case ISD::SETLT: in IntegerExpandSetCCOperands()
2599 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || in IntegerExpandSetCCOperands()
2834 ISD::SETLT); in ExpandIntOp_UINT_TO_FP()
DLegalizeDAG.cpp1595 ISD::SETLT); in ExpandFCOPYSIGN()
1718 case ISD::SETLT: in LegalizeSetCCCondCode()
2511 Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT); in ExpandLegalINT_TO_FP()
2550 ISD::SETLT); in ExpandLegalINT_TO_FP()
3212 DAG.getConstant(0, NVT), Ret, ISD::SETLT)); in ExpandNode()
3226 Tmp1, ISD::SETLT); in ExpandNode()
/external/llvm/lib/Target/R600/
DAMDGPUISelLowering.cpp984 case ISD::SETLT: { in CombineMinMax()
1390 ISD::SETLT); in LowerSDIV32()
1397 ISD::SETLT); in LowerSDIV32()
1474 SDValue r10 = DAG.getSetCC(DL, OVT, r0, DAG.getConstant(0, OVT), ISD::SETLT); in LowerSREM32()
1477 SDValue r11 = DAG.getSetCC(DL, OVT, r1, DAG.getConstant(0, OVT), ISD::SETLT); in LowerSREM32()
1639 SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT); in LowerSDIVREM()
1640 SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT); in LowerSDIVREM()
1736 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT); in LowerFTRUNC()
DAMDGPUInstructions.td78 [{return N->get() == ISD::SETOLT || N->get() == ISD::SETLT;}]
109 def COND_SLT : PatLeaf <(cond), [{return N->get() == ISD::SETLT;}]>;
DR600ISelLowering.cpp47 setCondCodeAction(ISD::SETLT, MVT::f32, Expand); in R600TargetLowering()
59 setCondCodeAction(ISD::SETLT, MVT::i32, Expand); in R600TargetLowering()
/external/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp603 case ISD::SETLT: return PPC::PRED_LT; in getPredicateForSetCC()
626 case ISD::SETLT: return 0; // Bit #0 = SETOLT in getCRIdxForSetCC()
672 case ISD::SETLT: in getVCmpInst()
773 case ISD::SETLT: { in SelectSETCC()
806 case ISD::SETLT: { in SelectSETCC()
848 case ISD::SETLT: in SelectSETCC()
DPPCInstrInfo.td2496 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)),
2593 defm : ExtSetCCPat<SETLT,
2625 defm : ExtSetCCPat<SETLT,
2660 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)),
2705 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)),
2728 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)),
2773 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)),
2796 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETLT)),
2827 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETLT)),
2863 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)),
[all …]
/external/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp955 case ISD::SETLT: in isLegalDSPCondCode()
1004 if (CondCode == ISD::SETLT || CondCode == ISD::SETLE) in performVSELECTCombine()
1711 Op->getOperand(2), ISD::SETLT); in lowerINTRINSIC_WO_CHAIN()
1717 lowerMSASplatImm(Op, 2, DAG), ISD::SETLT); in lowerINTRINSIC_WO_CHAIN()
DMipsDSPInstrInfo.td1361 def : DSPSetCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>;
1374 def : DSPSelectCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>;
/external/llvm/include/llvm/Target/
DTargetSelectionDAG.td511 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
875 (setcc node:$lhs, node:$rhs, SETLT)>;
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp1146 case ISD::SETLT: return ARMCC::LT; in IntCCToARMCC()
1175 case ISD::SETLT: in FPCCToARMCC()
3149 case ISD::SETLT: in getARMCmp()
3152 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT; in getARMCmp()
3166 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE; in getARMCmp()
4302 case ISD::SETLT: Swap = true; // Fallthrough in LowerVSETCC()
4338 case ISD::SETLT: Swap = true; in LowerVSETCC()
9510 case ISD::SETLT: in PerformSELECT_CCCombine()
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp863 case ISD::SETLT: in changeIntCCToAArch64CC()
924 case ISD::SETLT: in changeFPCCToAArch64CC()
1030 case ISD::SETLT: in getAArch64Cmp()
1036 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT; in getAArch64Cmp()
1057 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE; in getAArch64Cmp()
3357 case ISD::SETLT: in LowerSELECT_CC()
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp3548 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { in TranslateX86CC()
3552 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { in TranslateX86CC()
3564 case ISD::SETLT: return X86::COND_L; in TranslateX86CC()
3611 case ISD::SETLT: return X86::COND_B; in TranslateX86CC()
10955 ISD::SETLT); in LowerUINT_TO_FP()
12039 case ISD::SETLT: in translateX86FSETCC()
12114 case ISD::SETLT: Swap = true; //fall-through in LowerIntVSETCC_AVX512()
12239 case ISD::SETLT: Swap = true; in LowerVSETCC()
13520 CC = ISD::SETLT; in LowerINTRINSIC_WO_CHAIN()
13550 CC = ISD::SETLT; in LowerINTRINSIC_WO_CHAIN()
[all …]
/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp876 case ISD::SETLT: in EmitCMP()

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