| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 769 SETOLT, // 0 1 0 0 True if ordered and less than enumerator
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| /external/llvm/lib/CodeGen/ |
| D | Analysis.cpp | 157 case FCmpInst::FCMP_OLT: return ISD::SETOLT; in getFCmpCondCode()
177 case ISD::SETOLT: case ISD::SETULT: return ISD::SETLT; in getFCmpCodeWithoutNaN()
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| D | AMDGPUInstructions.td | 66 case ISD::SETOLT: case ISD::SETULT:
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| D | AMDILISelLowering.cpp | 131 setOperationAction(ISD::SETOLT, VT, Expand); in InitAMDILLowering()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDGPUInstructions.td | 66 case ISD::SETOLT: case ISD::SETULT:
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| D | AMDILISelLowering.cpp | 131 setOperationAction(ISD::SETOLT, VT, Expand); in InitAMDILLowering()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1140 setCondCodeAction(ISD::SETOLT, MVT::f32, Legal); in HexagonTargetLowering()
1141 setCondCodeAction(ISD::SETOLT, MVT::f64, Legal); in HexagonTargetLowering()
1246 setCondCodeAction(ISD::SETOLT, MVT::f64, Expand); in HexagonTargetLowering()
1249 setCondCodeAction(ISD::SETOLT, MVT::f32, Expand); in HexagonTargetLowering()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 602 case ISD::SETOLT: in getPredicateForSetCC()
625 case ISD::SETOLT: in getCRIdxForSetCC()
704 case ISD::SETOLT: in getVCmpInst()
849 case ISD::SETOLT: in SelectSETCC()
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| D | PPCInstrInfo.td | 2794 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOLT)),
2825 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOLT)),
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 301 case ISD::SETOLT: return "setolt"; in getOperationName()
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| D | TargetLowering.cpp | 143 case ISD::SETOLT: in softenSetCCOperands()
1772 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT); in SimplifySetCC()
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| D | SelectionDAG.cpp | 342 case ISD::SETOLT: Result = ISD::SETULT ; break; // SETULT & SETNE in getSetCCAndOperation()
1809 case ISD::SETOLT: in FoldSetCC()
1857 case ISD::SETOLT: return getConstant(R==APFloat::cmpLessThan, VT); in FoldSetCC()
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| D | LegalizeDAG.cpp | 1696 case ISD::SETOLT: in LegalizeSetCCCondCode()
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| /external/llvm/lib/Target/R600/ |
| D | AMDGPUInstructions.td | 78 [{return N->get() == ISD::SETOLT || N->get() == ISD::SETLT;}]
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| D | AMDGPUISelLowering.cpp | 982 case ISD::SETOLT: in CombineMinMax()
1791 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOLT); in LowerFFLOOR()
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| D | R600ISelLowering.cpp | 49 setCondCodeAction(ISD::SETOLT, MVT::f32, Expand); in R600TargetLowering()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 505 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
847 (setcc node:$lhs, node:$rhs, SETOLT)>;
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 1167 case ISD::SETOLT: CondCode = ARMCC::MI; break; in FPCCToARMCC()
3382 else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT || in checkVSELConstraints()
3388 if (CC == ISD::SETOLE || CC == ISD::SETULE || CC == ISD::SETOLT || in checkVSELConstraints()
3475 if (CC == ISD::SETOLT || CC == ISD::SETULT) in LowerSELECT_CC()
4301 case ISD::SETOLT: in LowerVSETCC()
9508 case ISD::SETOLT: in PerformSELECT_CCCombine()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXVector.td | 958 (setcc node:$lhs, node:$rhs, SETOLT)>;
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| /external/llvm/lib/Target/Mips/ |
| D | MipsMSAInstrInfo.td | 177 def vfsetolt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLT>;
178 def vfsetolt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLT>;
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| D | MipsSEISelLowering.cpp | 1791 Op->getOperand(2), ISD::SETOLT); in lowerINTRINSIC_WO_CHAIN()
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| D | MipsISelLowering.cpp | 472 case ISD::SETOLT: return Mips::FCOND_OLT; in condCodeToFCC()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1350 case ISD::SETOLT: return SPCC::FCC_L; in FPCondCCodeToFCC()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 898 case ISD::SETOLT: in changeFPCCToAArch64CC()
3361 case ISD::SETOLT: in LowerSELECT_CC()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 3585 case ISD::SETOLT: in TranslateX86CC()
3603 case ISD::SETOLT: // flipped in TranslateX86CC()
12040 case ISD::SETOLT: SSECC = 1; break; in translateX86FSETCC()
19262 case ISD::SETOLT: in PerformSELECTCombine()
19354 case ISD::SETOLT: in PerformSELECTCombine()
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