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Searched refs:SETUGE (Results 1 – 25 of 35) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h776 SETUGE, // 1 0 1 1 True if unordered, greater than, or equal enumerator
803 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
/external/llvm/lib/CodeGen/
DAnalysis.cpp164 case FCmpInst::FCMP_UGE: return ISD::SETUGE; in getFCmpCondCode()
180 case ISD::SETOGE: case ISD::SETUGE: return ISD::SETGE; in getFCmpCodeWithoutNaN()
195 case ICmpInst::ICMP_UGE: return ISD::SETUGE; in getICmpCondCode()
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
DAMDGPUInstructions.td59 case ISD::SETOGE: case ISD::SETUGE:
DAMDILISelLowering.cpp136 setOperationAction(ISD::SETUGE, VT, Expand); in InitAMDILLowering()
DR600Instructions.td441 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGE))]
/external/mesa3d/src/gallium/drivers/radeon/
DAMDGPUInstructions.td59 case ISD::SETOGE: case ISD::SETUGE:
DAMDILISelLowering.cpp136 setOperationAction(ISD::SETUGE, VT, Expand); in InitAMDILLowering()
DR600Instructions.td441 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGE))]
/external/llvm/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp178 case ISD::SETUGE: in softenSetCCOperands()
1391 case ISD::SETUGE: in SimplifySetCC()
1414 case ISD::SETUGE: in SimplifySetCC()
1560 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { in SimplifySetCC()
1592 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) in SimplifySetCC()
1682 } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE || in SimplifySetCC()
1695 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; in SimplifySetCC()
1766 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE); in SimplifySetCC()
1984 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X in SimplifySetCC()
DSelectionDAGDumper.cpp309 case ISD::SETUGE: return "setuge"; in getOperationName()
DLegalizeIntegerTypes.cpp867 case ISD::SETUGE: in PromoteSetCCOperands()
2564 case ISD::SETUGE: LowCC = ISD::SETUGE; break; in IntegerExpandSetCCOperands()
2597 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || in IntegerExpandSetCCOperands()
/external/llvm/lib/Target/Hexagon/
DHexagonSelectCCInfo.td68 IntRegs:$fval, SETUGE)),
DHexagonISelLowering.cpp1130 setCondCodeAction(ISD::SETUGE, MVT::f32, Legal); in HexagonTargetLowering()
1131 setCondCodeAction(ISD::SETUGE, MVT::f64, Legal); in HexagonTargetLowering()
/external/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp608 case ISD::SETUGE: in getPredicateForSetCC()
632 case ISD::SETUGE: in getCRIdxForSetCC()
689 case ISD::SETUGE: in getVCmpInst()
858 case ISD::SETUGE: { in SelectSETCC()
DPPCInstrInfo.td2508 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)),
2686 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)),
2714 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)),
2754 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)),
2782 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)),
2809 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)),
2840 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)),
/external/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp193 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand); in MipsSETargetLowering()
198 setCondCodeAction(ISD::SETUGE, MVT::f64, Expand); in MipsSETargetLowering()
286 setCondCodeAction(ISD::SETUGE, Ty, Expand); in addMSAIntType()
322 setCondCodeAction(ISD::SETUGE, Ty, Expand); in addMSAFloatType()
962 case ISD::SETUGE: return !IsV216; in isLegalDSPCondCode()
DMipsDSPInstrInfo.td1370 def : DSPSetCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
1383 def : DSPSelectCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
/external/llvm/lib/Target/R600/
DAMDGPUInstructions.td99 def COND_UGE : PatLeaf <(cond), [{return N->get() == ISD::SETUGE;}]>;
DAMDGPUISelLowering.cpp990 case ISD::SETUGE: in CombineMinMax()
1577 ISD::SETUGE); in LowerUDIVREM()
1583 ISD::SETUGE); in LowerUDIVREM()
DSIISelLowering.cpp60 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand); in SITargetLowering()
67 setCondCodeAction(ISD::SETUGE, MVT::f64, Expand); in SITargetLowering()
/external/llvm/include/llvm/Target/
DTargetSelectionDAG.td507 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
861 (setcc node:$lhs, node:$rhs, SETUGE)>;
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp1149 case ISD::SETUGE: return ARMCC::HS; in IntCCToARMCC()
1174 case ISD::SETUGE: CondCode = ARMCC::PL; break; in FPCCToARMCC()
3157 case ISD::SETUGE: in getARMCmp()
3173 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; in getARMCmp()
3377 if (CC == ISD::SETUGE || CC == ISD::SETOGE || CC == ISD::SETOLE || in checkVSELConstraints()
3400 if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE || in checkVSELConstraints()
4309 case ISD::SETUGE: Swap = true; // Fallthrough in LowerVSETCC()
4345 case ISD::SETUGE: Opc = ARMISD::VCGEU; break; in LowerVSETCC()
9535 case ISD::SETUGE: in PerformSELECT_CCCombine()
9539 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE); in PerformSELECT_CCCombine()
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/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp869 case ISD::SETUGE: in changeIntCCToAArch64CC()
921 case ISD::SETUGE: in changeFPCCToAArch64CC()
963 case ISD::SETUGE: in changeVectorFPCCToAArch64CC()
1042 case ISD::SETUGE: in getAArch64Cmp()
1068 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; in getAArch64Cmp()
3352 case ISD::SETUGE: in LowerSELECT_CC()
/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp837 case ISD::SETUGE: in EmitCMP()
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp3570 case ISD::SETUGE: return X86::COND_AE; in TranslateX86CC()
3588 case ISD::SETUGE: in TranslateX86CC()
3612 case ISD::SETUGE: // flipped in TranslateX86CC()
12049 case ISD::SETUGE: SSECC = 5; break; in translateX86FSETCC()
12117 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT in LowerIntVSETCC_AVX512()
12247 case ISD::SETUGE: Swap = true; in LowerVSETCC()
12262 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break; in LowerVSETCC()
12292 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break; in LowerVSETCC()
19132 case ISD::SETUGE: in matchIntegerMINMAX()
19150 case ISD::SETUGE: in matchIntegerMINMAX()
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