| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 45 SXTB, enumerator
64 case AArch64_AM::SXTB: return "sxtb"; in getShiftExtendName()
131 case 4: return AArch64_AM::SXTB; in getExtendType()
158 case AArch64_AM::SXTB: return 4; break; in getExtendEncoding()
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| /external/vixl/test/ |
| D | test-assembler-a64.cc | 224 __ Add(sp, sp, Operand(x17, SXTB)); in TEST()
271 __ Mvn(x11, Operand(x2, SXTB, 1)); in TEST()
437 __ Mov(x24, Operand(x13, SXTB, 1)); in TEST()
525 __ Orr(w10, w0, Operand(w1, SXTB)); in TEST()
614 __ Orn(w10, w0, Operand(w1, SXTB)); in TEST()
681 __ And(w10, w0, Operand(w1, SXTB)); in TEST()
819 __ Bic(w10, w0, Operand(w1, SXTB)); in TEST()
943 __ Eor(w10, w0, Operand(w1, SXTB)); in TEST()
1010 __ Eon(w10, w0, Operand(w1, SXTB)); in TEST()
2977 __ Add(x14, x0, Operand(x1, SXTB, 0)); in TEST()
[all …]
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| D | test-disasm-a64.cc | 343 COMPARE(adds(w15, w16, Operand(w17, SXTB, 4)), "adds w15, w16, w17, sxtb #4"); in TEST()
344 COMPARE(add(x18, x19, Operand(x20, SXTB, 3)), "add x18, x19, w20, sxtb #3"); in TEST()
369 COMPARE(subs(w15, w16, Operand(w17, SXTB, 4)), "subs w15, w16, w17, sxtb #4"); in TEST()
370 COMPARE(sub(x18, x19, Operand(x20, SXTB, 3)), "sub x18, x19, w20, sxtb #3"); in TEST()
374 COMPARE(cmp(w0, Operand(w1, SXTB, 1)), "cmp w0, w1, sxtb #1"); in TEST()
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| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 503 # SXTB/SXTH
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| D | invalid-armv7.txt | 330 # A8.6.223 SXTB
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| D | thumb2.txt | 2157 # SXTB
2211 # SXTB
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| /external/chromium_org/v8/test/cctest/ |
| D | test-assembler-arm64.cc | 258 __ Add(csp, csp, Operand(x17, SXTB)); in TEST()
306 __ Mvn(x11, Operand(x2, SXTB, 1)); in TEST()
379 __ Mov(x24, Operand(x13, SXTB, 1)); in TEST()
566 __ Orr(w10, w0, Operand(w1, SXTB)); in TEST()
663 __ Orn(w10, w0, Operand(w1, SXTB)); in TEST()
732 __ And(w10, w0, Operand(w1, SXTB)); in TEST()
873 __ Bic(w10, w0, Operand(w1, SXTB)); in TEST()
1001 __ Eor(w10, w0, Operand(w1, SXTB)); in TEST()
1070 __ Eon(w10, w0, Operand(w1, SXTB)); in TEST()
3653 __ Add(x14, x0, Operand(x1, SXTB, 0)); in TEST()
[all …]
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| D | test-disasm-arm64.cc | 382 COMPARE(adds(w15, w16, Operand(w17, SXTB, 4)), "adds w15, w16, w17, sxtb #4"); in TEST_()
383 COMPARE(add(x18, x19, Operand(x20, SXTB, 3)), "add x18, x19, w20, sxtb #3"); in TEST_()
408 COMPARE(subs(w15, w16, Operand(w17, SXTB, 4)), "subs w15, w16, w17, sxtb #4"); in TEST_()
409 COMPARE(sub(x18, x19, Operand(x20, SXTB, 3)), "sub x18, x19, w20, sxtb #3"); in TEST_()
413 COMPARE(cmp(w0, Operand(w1, SXTB, 1)), "cmp w0, w1, sxtb #1"); in TEST_()
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| /external/vixl/src/a64/ |
| D | simulator-a64.cc | 344 case SXTB: in ExtendValue()
791 set_wreg(srcdst, ExtendValue(kWRegSize, MemoryRead8(address), SXTB)); in LoadStoreHelper()
795 set_xreg(srcdst, ExtendValue(kXRegSize, MemoryRead8(address), SXTB)); in LoadStoreHelper()
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| D | constants-a64.h | 236 SXTB = 4, enumerator
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| D | assembler-a64.cc | 1788 case SXTB: in EmitExtendShift()
|
| /external/llvm/test/MC/ARM/ |
| D | basic-thumb-instructions.s | 638 @ SXTB/SXTH
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| D | basic-thumb2-instructions.s | 3055 @ SXTB
3113 @ SXTB
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| /external/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 463 SXTB, enumerator
|
| /external/chromium_org/v8/src/arm64/ |
| D | constants-arm64.h | 346 SXTB = 4, enumerator
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| D | assembler-arm64.cc | 2403 case SXTB: in EmitExtendShift()
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| D | simulator-arm64.cc | 932 case SXTB: in ExtendValue()
|
| /external/pcre/dist/sljit/ |
| D | sljitNativeARM_T2_32.c | 159 #define SXTB 0xb240 macro
701 return push_inst16(compiler, SXTB | RD3(dst) | RN3(arg2)); in emit_op_imm()
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| D | sljitNativeARM_32.c | 121 #define SXTB 0xe6af0070 macro
1027 return push_inst(compiler, (op == SLJIT_MOV_UB ? UXTB : SXTB) | RD(dst) | RM(src2)); in emit_single_op()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.td | 469 defm SXTB : ALU32_2op_base<"sxtb">, PredNewRel;
481 (SXTB IntRegs:$src1)>;
2226 // Map from Rdd = sign_extend_inreg(Rss, i8) -> Rdd = SXTW(SXTB(Rss.lo)).
2228 (i64 (SXTW (i32 (SXTB (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
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| D | HexagonInstrInfo.cpp | 718 case Hexagon::SXTB: in isPredicable()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 2647 /* 8 bit sext */ { { ARM::SXTB , 0, ARM_AM::no_shift, 0 }, in ARMEmitIntExt()
2892 { { ARM::SXTB, ARM::t2SXTB }, 0, 0, MVT::i8 },
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| D | ARMScheduleSwift.td | 1194 (instregex "SXTB", "SXTH", "SXTB16", "UXTB", "UXTH", "UXTB16",
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| D | ARMInstrInfo.td | 3277 def SXTB : AI_ext_rrot<0b01101010,
5332 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
5435 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 951 return (ET == AArch64_AM::UXTB || ET == AArch64_AM::SXTB || in isExtend()
2289 .Case("sxtb", AArch64_AM::SXTB) in tryParseOptionalShiftExtend()
|