| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 46 SXTH, enumerator
65 case AArch64_AM::SXTH: return "sxth"; in getShiftExtendName()
132 case 5: return AArch64_AM::SXTH; in getExtendType()
159 case AArch64_AM::SXTH: return 5; break; in getExtendEncoding()
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| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 503 # SXTB/SXTH
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| D | thumb2.txt | 2193 # SXTH
2247 # SXTH
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| /external/vixl/test/ |
| D | test-assembler-a64.cc | 273 __ Mvn(x13, Operand(x2, SXTH, 3)); in TEST()
439 __ Mov(x26, Operand(x13, SXTH, 3)); in TEST()
526 __ Orr(x11, x0, Operand(x1, SXTH, 1)); in TEST()
615 __ Orn(x11, x0, Operand(x1, SXTH, 1)); in TEST()
682 __ And(x11, x0, Operand(x1, SXTH, 1)); in TEST()
820 __ Bic(x11, x0, Operand(x1, SXTH, 1)); in TEST()
944 __ Eor(x11, x0, Operand(x1, SXTH, 1)); in TEST()
1011 __ Eon(x11, x0, Operand(x1, SXTH, 1)); in TEST()
2979 __ Add(x16, x0, Operand(x1, SXTH, 2)); in TEST()
2983 __ Add(x20, x0, Operand(x2, SXTH, 2)); in TEST()
[all …]
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| D | test-disasm-a64.cc | 119 COMPARE(Mov(w14, Operand(w15, SXTH, 2)), "sbfiz w14, w15, #2, #16"); in TEST()
345 COMPARE(adds(w21, w22, Operand(w23, SXTH, 2)), "adds w21, w22, w23, sxth #2"); in TEST()
349 COMPARE(cmn(x2, Operand(x3, SXTH, 4)), "cmn x2, w3, sxth #4"); in TEST()
371 COMPARE(subs(w21, w22, Operand(w23, SXTH, 2)), "subs w21, w22, w23, sxth #2"); in TEST()
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| /external/chromium_org/v8/test/cctest/ |
| D | test-disasm-arm64.cc | 144 COMPARE(Mov(w14, Operand(w15, SXTH, 2)), "sbfiz w14, w15, #2, #16"); in TEST_()
384 COMPARE(adds(w21, w22, Operand(w23, SXTH, 2)), "adds w21, w22, w23, sxth #2"); in TEST_()
388 COMPARE(cmn(x2, Operand(x3, SXTH, 4)), "cmn x2, w3, sxth #4"); in TEST_()
410 COMPARE(subs(w21, w22, Operand(w23, SXTH, 2)), "subs w21, w22, w23, sxth #2"); in TEST_()
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| D | test-assembler-arm64.cc | 308 __ Mvn(x13, Operand(x2, SXTH, 3)); in TEST()
381 __ Mov(x26, Operand(x13, SXTH, 3)); in TEST()
567 __ Orr(x11, x0, Operand(x1, SXTH, 1)); in TEST()
664 __ Orn(x11, x0, Operand(x1, SXTH, 1)); in TEST()
733 __ And(x11, x0, Operand(x1, SXTH, 1)); in TEST()
874 __ Bic(x11, x0, Operand(x1, SXTH, 1)); in TEST()
1002 __ Eor(x11, x0, Operand(x1, SXTH, 1)); in TEST()
1071 __ Eon(x11, x0, Operand(x1, SXTH, 1)); in TEST()
3655 __ Add(x16, x0, Operand(x1, SXTH, 2)); in TEST()
3659 __ Add(x20, x0, Operand(x2, SXTH, 2)); in TEST()
[all …]
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| /external/vixl/src/a64/ |
| D | simulator-a64.cc | 347 case SXTH: in ExtendValue()
799 set_wreg(srcdst, ExtendValue(kWRegSize, MemoryRead16(address), SXTH)); in LoadStoreHelper()
803 set_xreg(srcdst, ExtendValue(kXRegSize, MemoryRead16(address), SXTH)); in LoadStoreHelper()
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| D | constants-a64.h | 237 SXTH = 5, enumerator
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| D | assembler-a64.cc | 1789 case SXTH: in EmitExtendShift()
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| /external/llvm/test/MC/ARM/ |
| D | basic-thumb-instructions.s | 638 @ SXTB/SXTH
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| D | basic-thumb2-instructions.s | 3093 @ SXTH
3149 @ SXTH
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| /external/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 464 SXTH, enumerator
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelDAGToDAG.cpp | 937 SDNode *SextNode = CurDAG->getMachineNode(Hexagon::SXTH, dl, in SelectSelect()
961 SDNode *SextNode = CurDAG->getMachineNode(Hexagon::SXTH, dl, in SelectSelect()
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| D | HexagonInstrInfo.td | 470 defm SXTH : ALU32_2op_base<"sxth">, PredNewRel;
484 (SXTH IntRegs:$src1)>;
2221 // Map from Rdd = sign_extend_inreg(Rss, i16) -> Rdd = SXTW(SXTH(Rss.lo)).
2223 (i64 (SXTW (i32 (SXTH (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
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| D | HexagonInstrInfo.cpp | 719 case Hexagon::SXTH: in isPredicable()
|
| /external/chromium_org/v8/src/arm64/ |
| D | constants-arm64.h | 347 SXTH = 5, enumerator
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| D | assembler-arm64.cc | 2404 case SXTH: in EmitExtendShift()
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| D | simulator-arm64.cc | 935 case SXTH: in ExtendValue()
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| /external/pcre/dist/sljit/ |
| D | sljitNativeARM_T2_32.c | 161 #define SXTH 0xb200 macro
713 return push_inst16(compiler, SXTH | RD3(dst) | RN3(arg2)); in emit_op_imm()
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| D | sljitNativeARM_32.c | 122 #define SXTH 0xe6bf0070 macro
1046 return push_inst(compiler, (op == SLJIT_MOV_UH ? UXTH : SXTH) | RD(dst) | RM(src2)); in emit_single_op()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 2649 /* 16 bit sext */ { { ARM::SXTH , 0, ARM_AM::no_shift, 0 }, in ARMEmitIntExt()
2889 { { ARM::SXTH, ARM::t2SXTH }, 0, 0, MVT::i16 },
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| D | ARMScheduleSwift.td | 1194 (instregex "SXTB", "SXTH", "SXTB16", "UXTB", "UXTH", "UXTB16",
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| D | ARMInstrInfo.td | 3279 def SXTH : AI_ext_rrot<0b01101011,
5333 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
5439 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 952 ET == AArch64_AM::UXTH || ET == AArch64_AM::SXTH || in isExtend()
2290 .Case("sxth", AArch64_AM::SXTH) in tryParseOptionalShiftExtend()
|