| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 48 SXTX, enumerator
67 case AArch64_AM::SXTX: return "sxtx"; in getShiftExtendName()
134 case 7: return AArch64_AM::SXTX; in getExtendType()
161 case AArch64_AM::SXTX: return 7; break; in getExtendEncoding()
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| /external/vixl/test/ |
| D | test-disasm-a64.cc | 347 COMPARE(adds(x27, x28, Operand(x29, SXTX)), "adds x27, x28, x29, sxtx"); in TEST()
373 COMPARE(subs(x27, x28, Operand(x29, SXTX)), "subs x27, x28, x29, sxtx"); in TEST()
870 COMPARE(ldr(w18, MemOperand(x19, x20, SXTX)), "ldr w18, [x19, x20, sxtx]"); in TEST()
871 COMPARE(ldr(w21, MemOperand(x22, x23, SXTX, 2)), in TEST()
880 COMPARE(ldr(x18, MemOperand(x19, x20, SXTX)), "ldr x18, [x19, x20, sxtx]"); in TEST()
881 COMPARE(ldr(x21, MemOperand(x22, x23, SXTX, 3)), in TEST()
891 COMPARE(str(w18, MemOperand(x19, x20, SXTX)), "str w18, [x19, x20, sxtx]"); in TEST()
892 COMPARE(str(w21, MemOperand(x22, x23, SXTX, 2)), in TEST()
901 COMPARE(str(x18, MemOperand(x19, x20, SXTX)), "str x18, [x19, x20, sxtx]"); in TEST()
902 COMPARE(str(x21, MemOperand(x22, x23, SXTX, 3)), in TEST()
[all …]
|
| D | test-assembler-a64.cc | 528 __ Orr(x13, x0, Operand(x1, SXTX, 3)); in TEST()
617 __ Orn(x13, x0, Operand(x1, SXTX, 3)); in TEST()
684 __ And(x13, x0, Operand(x1, SXTX, 3)); in TEST()
822 __ Bic(x13, x0, Operand(x1, SXTX, 3)); in TEST()
946 __ Eor(x13, x0, Operand(x1, SXTX, 3)); in TEST()
1013 __ Eon(x13, x0, Operand(x1, SXTX, 3)); in TEST()
3440 __ Adcs(x10, x0, Operand(x1, SXTX, 1)); in TEST()
|
| /external/chromium_org/v8/test/cctest/ |
| D | test-disasm-arm64.cc | 386 COMPARE(adds(cp, jssp, Operand(fp, SXTX)), "adds cp, jssp, fp, sxtx"); in TEST_()
412 COMPARE(subs(cp, jssp, Operand(fp, SXTX)), "subs cp, jssp, fp, sxtx"); in TEST_()
903 COMPARE(ldr(w18, MemOperand(x19, x20, SXTX)), "ldr w18, [x19, x20, sxtx]"); in TEST_()
904 COMPARE(ldr(w21, MemOperand(x22, x23, SXTX, 2)), in TEST_()
913 COMPARE(ldr(x18, MemOperand(x19, x20, SXTX)), "ldr x18, [x19, x20, sxtx]"); in TEST_()
914 COMPARE(ldr(x21, MemOperand(x22, x23, SXTX, 3)), in TEST_()
924 COMPARE(str(w18, MemOperand(x19, x20, SXTX)), "str w18, [x19, x20, sxtx]"); in TEST_()
925 COMPARE(str(w21, MemOperand(x22, x23, SXTX, 2)), in TEST_()
934 COMPARE(str(x18, MemOperand(x19, x20, SXTX)), "str x18, [x19, x20, sxtx]"); in TEST_()
935 COMPARE(str(x21, MemOperand(x22, x23, SXTX, 3)), in TEST_()
[all …]
|
| D | test-assembler-arm64.cc | 569 __ Orr(x13, x0, Operand(x1, SXTX, 3)); in TEST()
666 __ Orn(x13, x0, Operand(x1, SXTX, 3)); in TEST()
735 __ And(x13, x0, Operand(x1, SXTX, 3)); in TEST()
876 __ Bic(x13, x0, Operand(x1, SXTX, 3)); in TEST()
1004 __ Eor(x13, x0, Operand(x1, SXTX, 3)); in TEST()
1073 __ Eon(x13, x0, Operand(x1, SXTX, 3)); in TEST()
4130 __ Adcs(x10, x0, Operand(x1, SXTX, 1)); in TEST()
|
| /external/chromium_org/v8/src/arm64/ |
| D | assembler-arm64-inl.h | 361 DCHECK(reg.Is64Bits() || ((extend != SXTX) && (extend != UXTX)));
475 DCHECK((extend == UXTW) || (extend == SXTW) || (extend == SXTX));
478 DCHECK(regoffset.Is64Bits() || (extend != SXTX));
528 DCHECK((extend_ == UXTW) || (extend_ == SXTW) || (extend_ == SXTX));
529 DCHECK((regoffset_.Is64Bits() || (extend_ != SXTX)));
|
| D | disasm-arm64.cc | 148 const char *form = ((mode == UXTX) || (mode == SXTX)) ? in VisitAddSubExtended()
150 const char *form_cmp = ((mode == UXTX) || (mode == SXTX)) ? in VisitAddSubExtended()
|
| D | constants-arm64.h | 349 SXTX = 7 enumerator
|
| D | simulator-arm64.cc | 942 case SXTX: in ExtendValue()
1555 DCHECK((ext == UXTW) || (ext == UXTX) || (ext == SXTW) || (ext == SXTX)); in VisitLoadStoreRegisterOffset()
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| D | macro-assembler-arm64.cc | 147 ((operand.extend() != UXTX) && (operand.extend() != SXTX))); in LogicalMacro()
549 ((operand.extend() != UXTX) && (operand.extend() != SXTX))); in AddSubWithCarryMacro()
|
| D | assembler-arm64.cc | 2407 case SXTX: { in EmitExtendShift()
|
| /external/vixl/src/a64/ |
| D | assembler-a64.cc | 235 VIXL_ASSERT(reg.Is64Bits() || ((extend != SXTX) && (extend != UXTX))); in Operand()
285 VIXL_ASSERT((extend == UXTW) || (extend == SXTW) || (extend == SXTX)); in MemOperand()
288 VIXL_ASSERT(regoffset.Is64Bits() || (extend != SXTX)); in MemOperand()
336 VIXL_ASSERT((extend_ == UXTW) || (extend_ == SXTW) || (extend_ == SXTX)); in MemOperand()
337 VIXL_ASSERT((regoffset_.Is64Bits() || (extend_ != SXTX))); in MemOperand()
1792 case SXTX: { in EmitExtendShift()
|
| D | disasm-a64.cc | 155 const char *form = ((mode == UXTX) || (mode == SXTX)) ? in VisitAddSubExtended()
157 const char *form_cmp = ((mode == UXTX) || (mode == SXTX)) ? in VisitAddSubExtended()
|
| D | macro-assembler-a64.cc | 199 ((operand.extend() != UXTX) && (operand.extend() != SXTX))); in LogicalMacro()
703 ((operand.extend() != UXTX) && (operand.extend() != SXTX))); in AddSubWithCarryMacro()
|
| D | constants-a64.h | 239 SXTX = 7 enumerator
|
| D | simulator-a64.cc | 354 case SXTX: in ExtendValue()
764 VIXL_ASSERT((ext == UXTW) || (ext == UXTX) || (ext == SXTW) || (ext == SXTX)); in VisitLoadStoreRegisterOffset()
|
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 954 ET == AArch64_AM::UXTX || ET == AArch64_AM::SXTX || in isExtend()
964 return ET != AArch64_AM::UXTX && ET != AArch64_AM::SXTX; in isExtend64()
970 return (ET == AArch64_AM::UXTX || ET == AArch64_AM::SXTX || in isExtendLSL64()
979 return (ET == AArch64_AM::LSL || ET == AArch64_AM::SXTX) && in isMemXExtend()
1539 bool IsSigned = ET == AArch64_AM::SXTW || ET == AArch64_AM::SXTX; in addMemExtendOperands()
1551 bool IsSigned = ET == AArch64_AM::SXTW || ET == AArch64_AM::SXTX; in addMemExtend8Operands()
2292 .Case("sxtx", AArch64_AM::SXTX) in tryParseOptionalShiftExtend()
|
| /external/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 466 SXTX enumerator
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 566 assert(Ext != AArch64_AM::UXTX && Ext != AArch64_AM::SXTX); in SelectArithExtendedRegister()
|
| D | AArch64InstrFormats.td | 1667 // UXTX and SXTX only.
1732 // UXTX and SXTX only.
|