Searched refs:SuperRC (Results 1 – 8 of 8) sorted by relevance
| /external/llvm/lib/Target/R600/ |
| D | SIInstrInfo.h | 31 const TargetRegisterClass *SuperRC,
37 const TargetRegisterClass *SuperRC,
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| D | AMDGPUISelDAGToDAG.cpp | 140 const TargetRegisterClass *SuperRC = TM.getRegisterInfo()->getRegClass(RCID); in getOperandRegClass() local
144 return TM.getRegisterInfo()->getSubClassWithSubReg(SuperRC, SubRegIdx); in getOperandRegClass()
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| D | SIInstrInfo.cpp | 781 const TargetRegisterClass *SuperRC, in buildExtractSubReg() argument
787 unsigned NewSuperReg = MRI.createVirtualRegister(SuperRC); in buildExtractSubReg()
808 const TargetRegisterClass *SuperRC, in buildExtractSubRegOrImm() argument
821 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC, in buildExtractSubRegOrImm()
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| /external/llvm/lib/CodeGen/ |
| D | AggressiveAntiDepBreaker.cpp | 610 const TargetRegisterClass *SuperRC = in FindSuitableFreeRegisters() local
613 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC); in FindSuitableFreeRegisters()
621 if (RenameOrder.count(SuperRC) == 0) in FindSuitableFreeRegisters()
622 RenameOrder.insert(RenameOrderType::value_type(SuperRC, Order.size())); in FindSuitableFreeRegisters()
624 unsigned OrigR = RenameOrder[SuperRC]; in FindSuitableFreeRegisters()
690 RenameOrder.erase(SuperRC); in FindSuitableFreeRegisters()
691 RenameOrder.insert(RenameOrderType::value_type(SuperRC, R)); in FindSuitableFreeRegisters()
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| D | RegAllocGreedy.cpp | 1496 const MachineInstr *MI, unsigned Reg, const TargetRegisterClass *SuperRC, in getNumAllocatableRegsForConstraints() argument
1499 assert(SuperRC && "Invalid register class"); in getNumAllocatableRegsForConstraints()
1502 MI->getRegClassConstraintEffectForVReg(Reg, SuperRC, TII, TRI, in getNumAllocatableRegsForConstraints()
1535 const TargetRegisterClass *SuperRC = TRI->getLargestLegalSuperClass(CurRC); in tryInstructionSplit() local
1536 unsigned SuperRCNumAllocatableRegs = RCI.getNumAllocatableRegs(SuperRC); in tryInstructionSplit()
1545 getNumAllocatableRegsForConstraints(MI, VirtReg.reg, SuperRC, TII, in tryInstructionSplit()
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| D | TargetLoweringBase.cpp | 994 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); in findRepresentativeClass() local
996 if (SuperRC->getSize() <= BestRC->getSize()) in findRepresentativeClass()
998 if (!isLegalRC(SuperRC)) in findRepresentativeClass()
1000 BestRC = SuperRC; in findRepresentativeClass()
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| D | MachineVerifier.cpp | 933 const TargetRegisterClass *SuperRC = in visitMachineOperand() local
935 if (!SuperRC) { in visitMachineOperand()
939 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx); in visitMachineOperand()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.h | 333 CodeGenRegisterClass *SuperRC) { in addSuperRegClass() argument
334 SuperRegClasses[SubIdx].insert(SuperRC); in addSuperRegClass()
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