| /external/valgrind/main/none/tests/mips64/ |
| D | branch_and_jump_instructions.c | 130 #define TEST4(instruction, RDval, RSval, RD, RS) \ macro
212 TEST4("bgez", 0, 0, 2, 3); in main()
213 TEST4("bgez", 1, 1, 3, 4); in main()
214 TEST4("bgez", 2, 0xffffffff, 4, 5); in main()
215 TEST4("bgez", 3, 0xffffffff, 5, 6); in main()
216 TEST4("bgez", 4, 0xfffffffe, 6, 7); in main()
217 TEST4("bgez", 5, 0xffffffff, 7, 8); in main()
218 TEST4("bgez", 6, 0x5, 8, 9); in main()
219 TEST4("bgez", 7, -3, 9, 10); in main()
220 TEST4("bgez", 8, 125, 10, 11); in main()
[all …]
|
| D | move_instructions.c | 139 #define TEST4(instruction, offset, RTval, FD, FS, RT) \ macro
243 TEST4("movn.s $f0, $f2, $11", 0, 0, f0, f2, 11); in main()
244 TEST4("movn.s $f0, $f2, $11", 0, 1, f0, f2, 11); in main()
245 TEST4("movn.s $f0, $f2, $11", 8, 0xffff, f0, f2, 11); in main()
246 TEST4("movn.s $f0, $f2, $11", 16, -1, f0, f2, 11); in main()
247 TEST4("movn.s $f0, $f2, $11", 16, 5, f0, f2, 11); in main()
248 TEST4("movn.s $f0, $f2, $11", 24, 0, f0, f2, 11); in main()
249 TEST4("movn.s $f0, $f2, $11", 24, 0, f0, f2, 11); in main()
250 TEST4("movn.s $f0, $f2, $11", 32, 5, f0, f2, 11); in main()
251 TEST4("movn.s $f0, $f2, $11", 32, 125487, f0, f2, 11); in main()
[all …]
|
| D | arithmetic_instruction.c | 137 TEST4("ddiv $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1); in main()
140 TEST4("ddiv $v0, $v1", reg_val2[i], reg_val2[N-i-1], v0, v1); in main()
148 TEST4("ddivu $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1); in main()
151 TEST4("ddivu $v0, $v1", reg_val2[i], reg_val2[N-i-1], v0, v1); in main()
162 TEST4("div $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1); in main()
173 TEST4("divu $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1); in main()
179 TEST4("dmult $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1); in main()
180 TEST4("dmult $v0, $v1", reg_val2[i], reg_val2[N-i-1], v0, v1); in main()
185 TEST4("dmultu $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1); in main()
186 TEST4("dmultu $v0, $v1", reg_val2[i], reg_val2[N-i-1], v0, v1); in main()
[all …]
|
| D | fpu_load_store.c | 47 TEST4("sdc1", i); in main()
53 TEST4("swc1", i); in main()
|
| D | macro_load_store.h | 83 #define TEST4(instruction, offset) \ macro
|
| D | macro_int.h | 51 #define TEST4(instruction, RSval, RTval, RS, RT) \ macro
|
| /external/llvm/test/MC/AsmParser/ |
| D | directive_ascii.s | 25 # CHECK: TEST4:
27 TEST4: label
|
| D | directive_values.s | 25 TEST4: label
31 # CHECK: TEST4
|
| D | directive_fill.s | 29 # CHECK: TEST4
34 TEST4: label
|
| /external/llvm/test/MC/ARM/ |
| D | eh-directive-multiple-offsets.s | 100 @ TEST4: Check ".setfp fp, sp" and ".setfp fp, fp" directive.
102 .section .TEST4
122 @ CHECK: Name: .ARM.extab.TEST4
|
| D | eh-directive-pad.s | 131 @ TEST4
133 .section .TEST4
165 @ CHECK: Name: .ARM.extab.TEST4
|
| D | eh-directive-setfp.s | 141 @ TEST4
143 .section .TEST4
176 @ CHECK: Name: .ARM.extab.TEST4
|
| D | eh-directive-cantunwind-diagnostics.s | 75 @ TEST4: handlerdata + cantunwind
|
| D | eh-directive-save.s | 216 @ TEST4
218 .section .TEST4
292 @ CHECK: Name: .ARM.extab.TEST4
|
| D | eh-directive-setfp-diagnostics.s | 60 @ TEST4: .setfp with bad sp register
|
| /external/clang/test/Frontend/ |
| D | verify3.c | 36 #ifdef TEST4
|
| D | verify.c | 91 #ifdef TEST4
|
| /external/clang/test/CodeGenObjC/ |
| D | arc-unopt.m | 46 // CHECK-NEXT: [[T1:%.*]] = bitcast [[TEST4S]]* [[T0]] to [[TEST4:%.*]]*
47 // CHECK-NEXT: ret [[TEST4]]* [[T1]]
|
| /external/clang/test/CXX/basic/basic.start/basic.start.main/ |
| D | p2.cpp | 47 #elif TEST4
|
| /external/bison/data/m4sugar/ |
| D | m4sugar.m4 | 1781 # | m4_defun([TEST4], [4])
1782 # | m4_defun([TEST5], [5 TEST4 m4_require([TEST4])])
|