| /external/vixl/test/ |
| D | test-simulator-a64.cc | 202 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, n_index_shift)); in Test1Op_Helper()
306 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, index_shift)); in Test2Op_Helper()
310 __ Ldr(fm, MemOperand(inputs_base, index_m, UXTW, index_shift)); in Test2Op_Helper()
425 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, index_shift)); in Test3Op_Helper()
429 __ Ldr(fm, MemOperand(inputs_base, index_m, UXTW, index_shift)); in Test3Op_Helper()
433 __ Ldr(fa, MemOperand(inputs_base, index_a, UXTW, index_shift)); in Test3Op_Helper()
555 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, index_shift)); in TestCmp_Helper()
559 __ Ldr(fm, MemOperand(inputs_base, index_m, UXTW, index_shift)); in TestCmp_Helper()
679 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, index_shift)); in TestCmpZero_Helper()
792 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, n_index_shift)); in TestFPToInt_Helper()
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| D | test-disasm-a64.cc | 341 COMPARE(adds(x9, x10, Operand(x11, UXTW, 3)), "adds x9, x10, w11, uxtw #3"); in TEST()
353 COMPARE(add(wsp, wsp, Operand(w4, UXTW, 2)), "add wsp, wsp, w4, lsl #2"); in TEST()
367 COMPARE(subs(x9, x10, Operand(x11, UXTW, 3)), "subs x9, x10, w11, uxtw #3"); in TEST()
379 COMPARE(sub(wsp, wsp, Operand(w4, UXTW, 2)), "sub wsp, wsp, w4, lsl #2"); in TEST()
863 COMPARE(ldr(w0, MemOperand(x1, w2, UXTW)), "ldr w0, [x1, w2, uxtw]"); in TEST()
864 COMPARE(ldr(w3, MemOperand(x4, w5, UXTW, 2)), "ldr w3, [x4, w5, uxtw #2]"); in TEST()
873 COMPARE(ldr(x0, MemOperand(x1, w2, UXTW)), "ldr x0, [x1, w2, uxtw]"); in TEST()
874 COMPARE(ldr(x3, MemOperand(x4, w5, UXTW, 3)), "ldr x3, [x4, w5, uxtw #3]"); in TEST()
884 COMPARE(str(w0, MemOperand(x1, w2, UXTW)), "str w0, [x1, w2, uxtw]"); in TEST()
885 COMPARE(str(w3, MemOperand(x4, w5, UXTW, 2)), "str w3, [x4, w5, uxtw #2]"); in TEST()
[all …]
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| D | test-assembler-a64.cc | 274 __ Mvn(x14, Operand(w2, UXTW, 4)); in TEST()
440 __ Mov(x27, Operand(w13, UXTW, 4)); in TEST()
523 __ Orr(w8, w0, Operand(w1, UXTW, 2)); in TEST()
612 __ Orn(w8, w0, Operand(w1, UXTW, 2)); in TEST()
679 __ And(w8, w0, Operand(w1, UXTW, 2)); in TEST()
817 __ Bic(w8, w0, Operand(w1, UXTW, 2)); in TEST()
941 __ Eor(w8, w0, Operand(w1, UXTW, 2)); in TEST()
1008 __ Eon(w8, w0, Operand(w1, UXTW, 2)); in TEST()
2975 __ Add(x13, x0, Operand(x1, UXTW, 4)); in TEST()
3159 __ Neg(w13, Operand(w0, UXTW, 4)); in TEST()
[all …]
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| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 42 UXTW, enumerator
62 case AArch64_AM::UXTW: return "uxtw"; in getShiftExtendName()
129 case 2: return AArch64_AM::UXTW; in getExtendType()
156 case AArch64_AM::UXTW: return 2; break; in getExtendEncoding()
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| /external/chromium_org/v8/test/cctest/ |
| D | test-disasm-arm64.cc | 380 COMPARE(adds(x9, x10, Operand(x11, UXTW, 3)), "adds x9, x10, w11, uxtw #3"); in TEST_()
392 COMPARE(add(wcsp, wcsp, Operand(w4, UXTW, 2)), "add wcsp, wcsp, w4, lsl #2"); in TEST_()
406 COMPARE(subs(x9, x10, Operand(x11, UXTW, 3)), "subs x9, x10, w11, uxtw #3"); in TEST_()
418 COMPARE(sub(wcsp, wcsp, Operand(w4, UXTW, 2)), "sub wcsp, wcsp, w4, lsl #2"); in TEST_()
896 COMPARE(ldr(w0, MemOperand(x1, w2, UXTW)), "ldr w0, [x1, w2, uxtw]"); in TEST_()
897 COMPARE(ldr(w3, MemOperand(x4, w5, UXTW, 2)), "ldr w3, [x4, w5, uxtw #2]"); in TEST_()
906 COMPARE(ldr(x0, MemOperand(x1, w2, UXTW)), "ldr x0, [x1, w2, uxtw]"); in TEST_()
907 COMPARE(ldr(x3, MemOperand(x4, w5, UXTW, 3)), "ldr x3, [x4, w5, uxtw #3]"); in TEST_()
917 COMPARE(str(w0, MemOperand(x1, w2, UXTW)), "str w0, [x1, w2, uxtw]"); in TEST_()
918 COMPARE(str(w3, MemOperand(x4, w5, UXTW, 2)), "str w3, [x4, w5, uxtw #2]"); in TEST_()
[all …]
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| D | test-assembler-arm64.cc | 309 __ Mvn(x14, Operand(w2, UXTW, 4)); in TEST()
382 __ Mov(x27, Operand(w13, UXTW, 4)); in TEST()
564 __ Orr(w8, w0, Operand(w1, UXTW, 2)); in TEST()
661 __ Orn(w8, w0, Operand(w1, UXTW, 2)); in TEST()
730 __ And(w8, w0, Operand(w1, UXTW, 2)); in TEST()
871 __ Bic(w8, w0, Operand(w1, UXTW, 2)); in TEST()
999 __ Eor(w8, w0, Operand(w1, UXTW, 2)); in TEST()
1068 __ Eon(w8, w0, Operand(w1, UXTW, 2)); in TEST()
3651 __ Add(x13, x0, Operand(x1, UXTW, 4)); in TEST()
3847 __ Neg(w13, Operand(w0, UXTW, 4)); in TEST()
[all …]
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| /external/chromium_org/v8/src/arm64/ |
| D | assembler-arm64-inl.h | 392 return Operand(reg_, reg_.Is64Bits() ? UXTX : UXTW, shift_amount_);
475 DCHECK((extend == UXTW) || (extend == SXTW) || (extend == SXTX));
528 DCHECK((extend_ == UXTW) || (extend_ == SXTW) || (extend_ == SXTX));
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| D | regexp-macro-assembler-arm64.cc | 194 __ Add(x10, code_pointer(), Operand(w10, UXTW)); in Backtrack()
539 __ Ldrb(w11, MemOperand(x11, w10, UXTW)); in CheckBitInTable()
620 __ Ldrb(w10, MemOperand(x10, current_character(), UXTW)); in CheckSpecialCharacterClass()
633 __ Ldrb(w10, MemOperand(x10, current_character(), UXTW)); in CheckSpecialCharacterClass()
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| D | disasm-arm64.cc | 1634 (((instr->ExtendMode() == UXTW) && (instr->SixtyFourBits() == 0)) || in SubstituteExtendField()
1658 char reg_type = ((ext == UXTW) || (ext == SXTW)) ? 'w' : 'x'; in SubstituteLSRegOffsetField()
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| D | constants-arm64.h | 344 UXTW = 2, enumerator
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| D | simulator-arm64.cc | 929 case UXTW: in ExtendValue()
1555 DCHECK((ext == UXTW) || (ext == UXTX) || (ext == SXTW) || (ext == SXTX)); in VisitLoadStoreRegisterOffset()
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| D | lithium-codegen-arm64.cc | 1485 __ Ldr(result, MemOperand(arguments, result, UXTW, kPointerSizeLog2)); in DoAccessArgumentsAt()
1487 __ Ldr(result, MemOperand(arguments, length, UXTW, kPointerSizeLog2)); in DoAccessArgumentsAt()
1494 __ Ldr(result, MemOperand(arguments, result, UXTW, kPointerSizeLog2)); in DoAccessArgumentsAt()
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| D | code-stubs-arm64.cc | 2407 __ Add(x2, start, Operand(w10, UXTW)); in Generate()
2412 __ Add(x3, x2, Operand(w10, UXTW)); in Generate()
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| D | assembler-arm64.cc | 2402 case UXTW: ubfm(rd, rn_, non_shift_bits, high_bit); break; in EmitExtendShift()
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| D | macro-assembler-arm64.cc | 1051 PushPreamble(Operand(count, UXTW, WhichPowerOf2(src.SizeInBytes()))); in PushMultipleTimes()
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| /external/vixl/src/a64/ |
| D | assembler-a64.cc | 266 return Operand(reg_, reg_.Is64Bits() ? UXTX : UXTW, shift_amount_); in ToExtendedRegister()
285 VIXL_ASSERT((extend == UXTW) || (extend == SXTW) || (extend == SXTX)); in MemOperand()
336 VIXL_ASSERT((extend_ == UXTW) || (extend_ == SXTW) || (extend_ == SXTX)); in MemOperand()
1787 case UXTW: ubfm(rd, rn_, non_shift_bits, high_bit); break; in EmitExtendShift()
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| D | disasm-a64.cc | 1626 (((instr->ExtendMode() == UXTW) && (instr->SixtyFourBits() == 0)) || in SubstituteExtendField()
1650 char reg_type = ((ext == UXTW) || (ext == SXTW)) ? 'w' : 'x'; in SubstituteLSRegOffsetField()
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| D | constants-a64.h | 234 UXTW = 2, enumerator
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| D | simulator-a64.cc | 341 case UXTW: in ExtendValue()
764 VIXL_ASSERT((ext == UXTW) || (ext == UXTX) || (ext == SXTW) || (ext == SXTX)); in VisitLoadStoreRegisterOffset()
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| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.cpp | 1006 if (ExtType == AArch64_AM::UXTW || ExtType == AArch64_AM::UXTX) { in printArithExtend()
1012 ExtType == AArch64_AM::UXTW) ) { in printArithExtend()
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| /external/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 460 UXTW, enumerator
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 953 ET == AArch64_AM::UXTW || ET == AArch64_AM::SXTW || in isExtend()
988 return (ET == AArch64_AM::UXTW || ET == AArch64_AM::SXTW) && in isMemWExtend()
1523 if (ET == AArch64_AM::LSL) ET = AArch64_AM::UXTW; in addExtendOperands()
2287 .Case("uxtw", AArch64_AM::UXTW) in tryParseOptionalShiftExtend()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 368 return AArch64_AM::UXTW; in getExtendTypeForNode()
386 return AArch64_AM::UXTW; in getExtendTypeForNode()
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| D | AArch64InstrFormats.td | 1681 GPR32sponly, GPR32sp, GPR32, 16>; // UXTW #0
1683 GPR32sp, GPR32sponly, GPR32, 16>; // UXTW #0
1773 GPR32, GPR32sponly, GPR32, 16>; // UXTW #0
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