| /external/llvm/include/llvm/MC/ |
| D | MCInstrItineraries.h | 198 unsigned UseClass, unsigned UseIdx) const { in hasPipelineForwarding() argument
208 if ((FirstUseIdx + UseIdx) >= LastUseIdx) in hasPipelineForwarding()
212 Forwardings[FirstUseIdx + UseIdx]; in hasPipelineForwarding()
219 unsigned UseClass, unsigned UseIdx) const { in getOperandLatency() argument
227 int UseCycle = getOperandCycle(UseClass, UseIdx); in getOperandLatency()
233 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx)) in getOperandLatency()
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| D | MCSubtargetInfo.h | 110 int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx, in getReadAdvanceCycles() argument
117 if (I->UseIdx < UseIdx) in getReadAdvanceCycles()
119 if (I->UseIdx > UseIdx) in getReadAdvanceCycles()
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| D | MCSchedule.h | 87 unsigned UseIdx; member
92 return UseIdx == Other.UseIdx && WriteResourceID == Other.WriteResourceID
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| /external/llvm/lib/CodeGen/ |
| D | LiveRangeEdit.cpp | 86 SlotIndex UseIdx) const { in allUsesAvailableAt()
88 UseIdx = UseIdx.getRegSlot(true); in allUsesAvailableAt()
109 if (SlotIndex::isSameInstr(OrigIdx, UseIdx)) in allUsesAvailableAt()
112 if (OVNI != li.getVNInfoAt(UseIdx)) in allUsesAvailableAt()
119 SlotIndex UseIdx, in canRematerializeAt() argument
142 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx)) in canRematerializeAt()
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| D | TargetSchedule.cpp | 145 unsigned UseIdx = 0; in findUseIdx() local
149 ++UseIdx; in findUseIdx()
151 return UseIdx; in findUseIdx()
203 unsigned UseIdx = findUseIdx(UseMI, UseOperIdx); in computeOperandLatency() local
204 int Advance = STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID); in computeOperandLatency()
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| D | TargetInstrInfo.cpp | 703 SDNode *UseNode, unsigned UseIdx) const { in getOperandLatency()
714 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
792 const MachineInstr *UseMI, unsigned UseIdx) const { in getOperandLatency()
795 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
829 const MachineInstr *UseMI, unsigned UseIdx) const { in computeOperandLatency()
839 OperLatency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx); in computeOperandLatency()
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| D | InlineSpiller.cpp | 856 SlotIndex UseIdx = LIS.getInstructionIndex(MI).getRegSlot(true); in reMaterializeFor() local
857 VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex()); in reMaterializeFor()
866 DEBUG(dbgs() << UseIdx << '\t' << *MI); in reMaterializeFor()
878 if (!Edit->canRematerializeAt(RM, UseIdx, false)) { in reMaterializeFor()
880 DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << *MI); in reMaterializeFor()
891 DEBUG(dbgs() << "\tcannot remat tied reg: " << UseIdx << '\t' << *MI); in reMaterializeFor()
922 DEBUG(dbgs() << "\t " << UseIdx << '\t' << *MI << '\n'); in reMaterializeFor()
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| D | SplitKit.h | 319 SlotIndex UseIdx,
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| D | MachineVerifier.cpp | 1007 SlotIndex UseIdx = LiveInts->getInstructionIndex(MI); in checkLiveness() local
1012 LiveQueryResult LRQ = LR->Query(UseIdx); in checkLiveness()
1015 *OS << UseIdx << " is not live in " << PrintRegUnit(*Units, TRI) in checkLiveness()
1030 LiveQueryResult LRQ = LI.Query(UseIdx); in checkLiveness()
1033 *OS << UseIdx << " is not live in " << LI << '\n'; in checkLiveness()
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| D | RegisterCoalescer.cpp | 627 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI); in removeCopyByCommutingDef() local
628 LiveInterval::iterator US = IntA.FindSegmentContaining(UseIdx); in removeCopyByCommutingDef()
679 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI).getRegSlot(true); in removeCopyByCommutingDef() local
680 LiveInterval::iterator US = IntA.FindSegmentContaining(UseIdx); in removeCopyByCommutingDef()
699 SlotIndex DefIdx = UseIdx.getRegSlot(); in removeCopyByCommutingDef()
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| D | TwoAddressInstructionPass.cpp | 1480 SlotIndex UseIdx = MIIdx.getRegSlot(IsEarlyClobber); in processTiedPairs() local
1481 if (I->end == UseIdx) in processTiedPairs()
1482 LI.removeSegment(LastCopyIdx, UseIdx); in processTiedPairs()
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| D | MachineInstr.cpp | 1177 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) { in tieOperands() argument
1179 MachineOperand &UseMO = getOperand(UseIdx); in tieOperands()
1196 DefMO.TiedTo = std::min(UseIdx + 1, TiedMax); in tieOperands()
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| D | SplitKit.cpp | 432 SlotIndex UseIdx, in defFromParent() argument
445 if (Edit->canRematerializeAt(RM, UseIdx, true)) { in defFromParent()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.h | 218 unsigned UseIdx) const override;
221 SDNode *UseNode, unsigned UseIdx) const override;
256 unsigned UseIdx, unsigned UseAlign) const;
260 unsigned UseIdx, unsigned UseAlign) const;
265 unsigned UseIdx, unsigned UseAlign) const;
280 unsigned UseIdx) const override;
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| D | ARMBaseInstrInfo.cpp | 3084 unsigned UseIdx, unsigned UseAlign) const { in getVSTMUseCycle() argument
3085 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; in getVSTMUseCycle()
3087 return ItinData->getOperandCycle(UseClass, UseIdx); in getVSTMUseCycle()
3124 unsigned UseIdx, unsigned UseAlign) const { in getSTMUseCycle() argument
3125 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; in getSTMUseCycle()
3127 return ItinData->getOperandCycle(UseClass, UseIdx); in getSTMUseCycle()
3154 unsigned UseIdx, unsigned UseAlign) const { in getOperandLatency() argument
3158 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands()) in getOperandLatency()
3159 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
3209 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx); in getOperandLatency()
[all …]
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.h | 101 unsigned UseIdx) const override;
104 SDNode *UseNode, unsigned UseIdx) const override { in getOperandLatency() argument
106 UseNode, UseIdx); in getOperandLatency()
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| D | PPCInstrInfo.cpp | 111 unsigned UseIdx) const { in getOperandLatency()
113 UseMI, UseIdx); in getOperandLatency()
1014 unsigned UseIdx; in FoldImmediate() local
1015 for (UseIdx = 0; UseIdx < UseMI->getNumOperands(); ++UseIdx) in FoldImmediate()
1016 if (UseMI->getOperand(UseIdx).isReg() && in FoldImmediate()
1017 UseMI->getOperand(UseIdx).getReg() == Reg) in FoldImmediate()
1020 assert(UseIdx < UseMI->getNumOperands() && "Cannot find Reg in UseMI"); in FoldImmediate()
1021 assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg"); in FoldImmediate()
1023 const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx]; in FoldImmediate()
1052 UseMI->getOperand(UseIdx).setReg(ZeroReg); in FoldImmediate()
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| /external/llvm/include/llvm/CodeGen/ |
| D | LiveRangeEdit.h | 88 SlotIndex UseIdx) const;
184 SlotIndex UseIdx,
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| D | MachineInstr.h | 930 void tieOperands(unsigned DefIdx, unsigned UseIdx);
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| /external/llvm/include/llvm/Target/ |
| D | TargetInstrInfo.h | 839 SDNode *UseNode, unsigned UseIdx) const;
852 unsigned UseIdx) const;
858 const MachineInstr *UseMI, unsigned UseIdx)
893 const MachineInstr *UseMI, unsigned UseIdx) const { in hasHighOperandLatency() argument
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| /external/llvm/utils/TableGen/ |
| D | SubtargetEmitter.cpp | 992 for (unsigned UseIdx = 0, EndIdx = Reads.size(); in GenSchedClassTables() local
993 UseIdx != EndIdx; ++UseIdx) { in GenSchedClassTables()
995 FindReadAdvance(SchedModels.getSchedRead(Reads[UseIdx]), ProcModel); in GenSchedClassTables()
1017 RAEntry.UseIdx = UseIdx; in GenSchedClassTables()
1129 OS << " {" << RAEntry.UseIdx << ", " in EmitSchedClassTables()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.h | 421 unsigned UseIdx) const override;
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| D | X86InstrInfo.cpp | 5393 const MachineInstr *UseMI, unsigned UseIdx) const { in hasHighOperandLatency()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 991 unsigned UseIdx = GroupIdx.back() + 1; in EmitSpecialNode() local
993 MIB->tieOperands(DefIdx + j, UseIdx + j); in EmitSpecialNode()
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