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Searched refs:base_reg (Results 1 – 22 of 22) sorted by relevance

/external/chromium_org/v8/src/x64/
Dcodegen-x64.h57 Register base_reg,
62 : base_reg_(base_reg), in base_reg_() argument
70 Register base_reg,
75 : base_reg_(base_reg), in base_reg_() argument
83 Register base_reg,
88 : base_reg_(base_reg), in base_reg_() argument
Ddisasm-x64.cc340 int base_reg(int low_bits) { return low_bits | ((rex_ & 0x01) << 3); } in base_reg() function in disasm::DisassemblerX64
1423 NameOfCPURegister(base_reg(current & 0x07))); in InstructionDecode()
1429 NameOfCPURegister(base_reg(current & 0x07))); in InstructionDecode()
1453 NameOfCPURegister(base_reg(current & 0x07)), in InstructionDecode()
Dmacro-assembler-x64.cc739 Register base_reg = r15; in CallApiFunctionAndReturn() local
740 Move(base_reg, next_address); in CallApiFunctionAndReturn()
741 movp(prev_next_address_reg, Operand(base_reg, kNextOffset)); in CallApiFunctionAndReturn()
742 movp(prev_limit_reg, Operand(base_reg, kLimitOffset)); in CallApiFunctionAndReturn()
743 addl(Operand(base_reg, kLevelOffset), Immediate(1)); in CallApiFunctionAndReturn()
790 subl(Operand(base_reg, kLevelOffset), Immediate(1)); in CallApiFunctionAndReturn()
791 movp(Operand(base_reg, kNextOffset), prev_next_address_reg); in CallApiFunctionAndReturn()
792 cmpp(prev_limit_reg, Operand(base_reg, kLimitOffset)); in CallApiFunctionAndReturn()
853 movp(Operand(base_reg, kLimitOffset), prev_limit_reg); in CallApiFunctionAndReturn()
Dassembler-x64.cc158 int base_reg = (has_sib ? operand.buf_[1] : modrm) & 0x07; in Operand() local
161 bool is_baseless = (mode == 0) && (base_reg == 0x05); // No base or RIP base. in Operand()
181 } else if (disp_value != 0 || (base_reg == 0x05)) { in Operand()
/external/lldb/include/lldb/Core/
DEmulateInstruction.h190 RegisterInfo base_reg; // base register number member
197 RegisterInfo base_reg; // base register for address calculation member
203 RegisterInfo base_reg; // base register for address calculation member
246 SetRegisterPlusOffset (RegisterInfo base_reg, in SetRegisterPlusOffset()
250 info.RegisterPlusOffset.reg = base_reg; in SetRegisterPlusOffset()
255 SetRegisterPlusIndirectOffset (RegisterInfo base_reg, in SetRegisterPlusIndirectOffset()
259 info.RegisterPlusIndirectOffset.base_reg = base_reg; in SetRegisterPlusIndirectOffset()
265 RegisterInfo base_reg, in SetRegisterToRegisterPlusOffset()
270 info.RegisterToRegisterPlusOffset.base_reg = base_reg; in SetRegisterToRegisterPlusOffset()
275 SetRegisterToRegisterPlusIndirectOffset (RegisterInfo base_reg, in SetRegisterToRegisterPlusIndirectOffset()
[all …]
/external/lldb/source/Plugins/Instruction/ARM/
DEmulateInstructionARM.cpp3964 RegisterInfo base_reg; in EmulateLDRRtRnImm() local
3965 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rn, base_reg); in EmulateLDRRtRnImm()
3970 ctx.SetRegisterPlusOffset (base_reg, (int32_t) (offset_addr - base)); in EmulateLDRRtRnImm()
3979 context.SetRegisterPlusOffset (base_reg, (int32_t) (offset_addr - base)); in EmulateLDRRtRnImm()
4097 RegisterInfo base_reg; in EmulateSTM() local
4098 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg); in EmulateSTM()
4122 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, offset); in EmulateSTM()
4222 RegisterInfo base_reg; in EmulateSTMDA() local
4223 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg); in EmulateSTMDA()
4247 … context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, Rn - (address + offset)); in EmulateSTMDA()
[all …]
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/
Dbrw_vec4_reg_allocate.cpp131 for (int base_reg = j; in brw_alloc_reg_set_for_classes() local
132 base_reg < j + class_sizes[i]; in brw_alloc_reg_set_for_classes()
133 base_reg++) { in brw_alloc_reg_set_for_classes()
134 ra_add_transitive_reg_conflict(brw->vs.regs, base_reg, reg); in brw_alloc_reg_set_for_classes()
Dbrw_fs_reg_allocate.cpp119 for (int base_reg = j; in brw_alloc_reg_set_for_classes() local
120 base_reg < j + class_sizes[i]; in brw_alloc_reg_set_for_classes()
121 base_reg++) { in brw_alloc_reg_set_for_classes()
122 ra_add_transitive_reg_conflict(brw->wm.regs, base_reg, reg); in brw_alloc_reg_set_for_classes()
Dbrw_blorp_blit.cpp493 void alloc_push_const_regs(int base_reg);
743 brw_blorp_blit_program::alloc_push_const_regs(int base_reg) in alloc_push_const_regs() argument
748 brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, base_reg, CONST_LOC(name) / 2) in alloc_push_const_regs()
Dbrw_wm_emit.c1323 GLuint base_reg, in fire_fb_write() argument
1343 brw_message_reg(base_reg + 1), in fire_fb_write()
1357 base_reg, in fire_fb_write()
/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_vec4_reg_allocate.cpp131 for (int base_reg = j; in brw_alloc_reg_set_for_classes() local
132 base_reg < j + class_sizes[i]; in brw_alloc_reg_set_for_classes()
133 base_reg++) { in brw_alloc_reg_set_for_classes()
134 ra_add_transitive_reg_conflict(brw->vs.regs, base_reg, reg); in brw_alloc_reg_set_for_classes()
Dbrw_fs_reg_allocate.cpp119 for (int base_reg = j; in brw_alloc_reg_set_for_classes() local
120 base_reg < j + class_sizes[i]; in brw_alloc_reg_set_for_classes()
121 base_reg++) { in brw_alloc_reg_set_for_classes()
122 ra_add_transitive_reg_conflict(brw->wm.regs, base_reg, reg); in brw_alloc_reg_set_for_classes()
Dbrw_blorp_blit.cpp493 void alloc_push_const_regs(int base_reg);
743 brw_blorp_blit_program::alloc_push_const_regs(int base_reg) in alloc_push_const_regs() argument
748 brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, base_reg, CONST_LOC(name) / 2) in alloc_push_const_regs()
Dbrw_wm_emit.c1323 GLuint base_reg, in fire_fb_write() argument
1343 brw_message_reg(base_reg + 1), in fire_fb_write()
1357 base_reg, in fire_fb_write()
/external/mesa3d/src/mesa/program/
Dregister_allocate.c219 unsigned int base_reg, unsigned int reg) in ra_add_transitive_reg_conflict() argument
223 ra_add_reg_conflict(regs, reg, base_reg); in ra_add_transitive_reg_conflict()
225 for (i = 0; i < regs->regs[base_reg].num_conflicts; i++) { in ra_add_transitive_reg_conflict()
226 ra_add_reg_conflict(regs, reg, regs->regs[base_reg].conflict_list[i]); in ra_add_transitive_reg_conflict()
Dregister_allocate.h44 unsigned int base_reg, unsigned int reg);
/external/chromium_org/third_party/mesa/src/src/mesa/program/
Dregister_allocate.c219 unsigned int base_reg, unsigned int reg) in ra_add_transitive_reg_conflict() argument
223 ra_add_reg_conflict(regs, reg, base_reg); in ra_add_transitive_reg_conflict()
225 for (i = 0; i < regs->regs[base_reg].num_conflicts; i++) { in ra_add_transitive_reg_conflict()
226 ra_add_reg_conflict(regs, reg, regs->regs[base_reg].conflict_list[i]); in ra_add_transitive_reg_conflict()
Dregister_allocate.h44 unsigned int base_reg, unsigned int reg);
/external/lldb/source/Core/
DEmulateInstruction.cpp516 info.RegisterPlusIndirectOffset.base_reg.name, in Dump()
524 info.RegisterToRegisterPlusOffset.base_reg.name, in Dump()
533 info.RegisterToRegisterPlusIndirectOffset.base_reg.name, in Dump()
/external/qemu/
Dgdbstub.c260 int base_reg; member
1393 if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) { in gdb_read_register()
1394 return r->get_reg(env, mem_buf, reg - r->base_reg); in gdb_read_register()
1409 if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) { in gdb_write_register()
1410 return r->set_reg(env, mem_buf, reg - r->base_reg); in gdb_write_register()
1431 s->base_reg = last_reg; in gdb_register_coprocessor()
1447 if (g_pos != s->base_reg) { in gdb_register_coprocessor()
1449 "Expected %d got %d\n", xml, g_pos, s->base_reg); in gdb_register_coprocessor()
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/radeon/
Dradeon_state_init.c423 uint32_t base_reg; in cube_emit_cs() local
435 case 1: base_reg = RADEON_PP_CUBIC_OFFSET_T1_0; break; in cube_emit_cs()
436 case 2: base_reg = RADEON_PP_CUBIC_OFFSET_T2_0; break; in cube_emit_cs()
438 case 0: base_reg = RADEON_PP_CUBIC_OFFSET_T0_0; break; in cube_emit_cs()
444 OUT_BATCH(CP_PACKET0(base_reg + (4 * j), 0)); in cube_emit_cs()
/external/mesa3d/src/mesa/drivers/dri/radeon/
Dradeon_state_init.c423 uint32_t base_reg; in cube_emit_cs() local
435 case 1: base_reg = RADEON_PP_CUBIC_OFFSET_T1_0; break; in cube_emit_cs()
436 case 2: base_reg = RADEON_PP_CUBIC_OFFSET_T2_0; break; in cube_emit_cs()
438 case 0: base_reg = RADEON_PP_CUBIC_OFFSET_T0_0; break; in cube_emit_cs()
444 OUT_BATCH(CP_PACKET0(base_reg + (4 * j), 0)); in cube_emit_cs()