Home
last modified time | relevance | path

Searched refs:bc1t (Results 1 – 25 of 36) sorted by relevance

12

/external/llvm/test/MC/Mips/
Dmips-bad-branches.s208 # CHECK: bc1t -131069
210 # CHECK: bc1t -131070
212 # CHECK: bc1t -131071
214 # CHECK: bc1t -131073
216 # CHECK: bc1t 131069
218 # CHECK: bc1t 131070
220 # CHECK: bc1t 131071
222 # CHECK: bc1t 131072
225 # CHECK: bc1t $fcc0, -131069
227 # CHECK: bc1t $fcc0, -131070
[all …]
Dmicromips-bad-branches.s112 # CHECK: bc1t -65535
114 # CHECK: bc1t -65537
116 # CHECK: bc1t 65535
118 # CHECK: bc1t 65536
121 # CHECK: bc1t $fcc0, -65535
123 # CHECK: bc1t $fcc0, -65537
125 # CHECK: bc1t $fcc0, 65535
127 # CHECK: bc1t $fcc0, 65536
213 bc1t -65535
214 bc1t -65536
[all …]
Dmips-jump-instructions.s15 # CHECK32: bc1t 1332 # encoding: [0x4d,0x01,0x01,0x45]
40 # CHECK64: bc1t 1332 # encoding: [0x4d,0x01,0x01,0x45]
67 bc1t 1332
Dmicromips-fpu-instructions.s26 # CHECK-EL: bc1t 1332 # encoding: [0xa0,0x43,0x9a,0x02]
89 # CHECK-EB: bc1t 1332 # encoding: [0x43,0xa0,0x02,0x9a]
149 bc1t 1332
/external/llvm/test/MC/Mips/mips32/
Dvalid.s19 bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
20 bc1t $fcc1, 4 # CHECK: bc1t $fcc1, 4 # encoding: [0x45,0x05,0x00,0x01]
21 bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
/external/llvm/test/MC/Mips/mips1/
Dvalid.s18 bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
19 bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
/external/llvm/test/MC/Mips/mips32r2/
Dvalid.s19 bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
20 bc1t $fcc1, 4 # CHECK: bc1t $fcc1, 4 # encoding: [0x45,0x05,0x00,0x01]
21 bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
/external/llvm/test/MC/Mips/mips4/
Dvalid.s19 bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
20 bc1t $fcc1, 4 # CHECK: bc1t $fcc1, 4 # encoding: [0x45,0x05,0x00,0x01]
21 bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
/external/llvm/test/MC/Mips/mips5/
Dvalid.s19 bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
20 bc1t $fcc1, 4 # CHECK: bc1t $fcc1, 4 # encoding: [0x45,0x05,0x00,0x01]
21 bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
/external/llvm/test/MC/Mips/mips2/
Dvalid.s18 bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
19 bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
Dinvalid-mips32.s9 … bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Dinvalid-mips32r2.s9 … bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
/external/llvm/test/MC/Mips/mips64/
Dvalid.s19 bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
20 bc1t $fcc1, 4 # CHECK: bc1t $fcc1, 4 # encoding: [0x45,0x05,0x00,0x01]
21 bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
/external/llvm/test/MC/Mips/mips64r2/
Dvalid.s19 bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
20 bc1t $fcc1, 4 # CHECK: bc1t $fcc1, 4 # encoding: [0x45,0x05,0x00,0x01]
21 bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
/external/llvm/test/MC/Mips/mips3/
Dvalid.s18 bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
19 bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
Dinvalid-mips4.s9 … bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Dinvalid-mips5.s9 … bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
/external/llvm/test/CodeGen/Mips/
Dfpbr.ll77 ; FCC: bc1t $BB2_2
165 ; FCC: bc1t $BB5_2
/external/llvm/test/MC/Disassembler/Mips/
Dmips32r2.txt41 # CHECK: bc1t 1332
44 # CHECK: bc1t $fcc7, 1332
Dmips32r2_le.txt41 # CHECK: bc1t 1332
44 # CHECK: bc1t $fcc7, 1332
Dmips32.txt41 # CHECK: bc1t 1332
44 # CHECK: bc1t $fcc7, 1332
Dmips32_le.txt41 # CHECK: bc1t 1332
44 # CHECK: bc1t $fcc7, 1332
/external/chromium_org/v8/src/mips/
Dassembler-mips.h940 void bc1t(int16_t offset, uint16_t cc = 0);
941 void bc1t(Label* L, uint16_t cc = 0) { bc1t(branch_offset(L, false)>>2, cc); }
/external/chromium_org/v8/src/mips64/
Dassembler-mips64.h974 void bc1t(int16_t offset, uint16_t cc = 0);
975 void bc1t(Label* L, uint16_t cc = 0) {
976 bc1t(branch_offset(L, false)>>2, cc);
/external/llvm/lib/Target/Mips/
DMicroMipsInstrFPU.td42 def BC1T_MM : MMRel, BC1F_FT<"bc1t", brtarget_mm, IIBranch, MIPS_BRANCH_T>,

12