Home
last modified time | relevance | path

Searched refs:dsrl (Results 1 – 25 of 37) sorted by relevance

12

/external/valgrind/main/none/tests/mips64/
Dshift_instructions.stdout.exp-mips649217 dsrl $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000
9218 dsrl $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f
9219 dsrl $a0, $a1, 0x0f :: rt 0x0, rs 0x0, imm 0x000f
9220 dsrl $s0, $s1, 0x03 :: rt 0x0, rs 0x0, imm 0x0003
9221 dsrl $t0, $t1, 0x00 :: rt 0x12bd6aa, rs 0x12bd6aa, imm 0x0000
9222 dsrl $t2, $t3, 0x1f :: rt 0x0, rs 0x12bd6aa, imm 0x001f
9223 dsrl $a0, $a1, 0x0f :: rt 0x257, rs 0x12bd6aa, imm 0x000f
9224 dsrl $s0, $s1, 0x03 :: rt 0x257ad5, rs 0x12bd6aa, imm 0x0003
9225 dsrl $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000
9226 dsrl $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f
[all …]
Dshift_instructions.stdout.exp-mips64r213825 dsrl $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000
13826 dsrl $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f
13827 dsrl $a0, $a1, 0x0f :: rt 0x0, rs 0x0, imm 0x000f
13828 dsrl $s0, $s1, 0x03 :: rt 0x0, rs 0x0, imm 0x0003
13829 dsrl $t0, $t1, 0x00 :: rt 0x12bd6aa, rs 0x12bd6aa, imm 0x0000
13830 dsrl $t2, $t3, 0x1f :: rt 0x0, rs 0x12bd6aa, imm 0x001f
13831 dsrl $a0, $a1, 0x0f :: rt 0x257, rs 0x12bd6aa, imm 0x000f
13832 dsrl $s0, $s1, 0x03 :: rt 0x257ad5, rs 0x12bd6aa, imm 0x0003
13833 dsrl $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000
13834 dsrl $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f
[all …]
/external/llvm/test/CodeGen/Mips/
Dmadd-msub.ll80 ; 64-DAG: dsrl $[[T1:[0-9]+]], $[[T0]], 32
82 ; 64-DAG: dsrl $[[T3:[0-9]+]], $[[T2]], 32
86 ; 64-DAG: dsrl $[[T6:[0-9]+]], $[[T5]], 32
90 ; 64R6-DAG: dsrl $[[T1:[0-9]+]], $[[T0]], 32
92 ; 64R6-DAG: dsrl $[[T3:[0-9]+]], $[[T2]], 32
95 ; 64R6-DAG: dsrl $[[T6:[0-9]+]], $[[T5]], 32
218 ; 64-DAG: dsrl $[[T1:[0-9]+]], $[[T0]], 32
220 ; 64-DAG: dsrl $[[T3:[0-9]+]], $[[T2]], 32
224 ; 64-DAG: dsrl $[[T6:[0-9]+]], $[[T5]], 32
228 ; 64R6-DAG: dsrl $[[T1:[0-9]+]], $[[T0]], 32
[all …]
Dmips64shift.ll40 ; CHECK: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 10
61 ; CHECK: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 40
Dmips64ext.ll8 ; CHECK: dsrl ${{[0-9]+}}, $[[R1]], 32
Dfcopysign-f32-f64.ll15 ; 64-DAG: dsrl $[[DSRL:[0-9]+]], ${{[0-9]+}}, 63
/external/llvm/test/MC/Mips/mips3/
Dvalid.s75 …dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0x…
76 …dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0x…
77 …dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x…
/external/llvm/test/MC/Mips/mips4/
Dvalid.s77 …dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0x…
78 …dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0x…
79 …dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x…
/external/llvm/test/MC/Mips/mips5/
Dvalid.s77 …dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0x…
78 …dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0x…
79 …dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x…
/external/llvm/test/MC/Mips/mips64/
Dvalid.s82 …dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0x…
83 …dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0x…
84 …dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x…
/external/llvm/test/MC/Mips/mips64r2/
Dvalid.s90 …dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0x…
91 …dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0x…
92 …dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x…
/external/llvm/test/MC/Mips/mips2/
Dinvalid-mips3.s35 …dsrl $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fea…
36 …dsrl $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fea…
37 …dsrl $s3,$6,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fea…
Dinvalid-mips5.s37 …dsrl $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
38 …dsrl $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
39 …dsrl $s3,$6,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
Dinvalid-mips4.s38 …dsrl $s3,$6,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
39 …dsrl $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
40 …dsrl $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
/external/chromium_org/v8/src/ic/mips64/
Dstub-cache-mips64.cc139 __ dsrl(scratch, scratch, kCacheIndexShift); in GenerateProbe() local
148 __ dsrl(at, name, kCacheIndexShift); in GenerateProbe() local
/external/llvm/test/MC/Mips/
Delf-gprel-32-64.s49 dsrl $3, $3, 32
Dmips64shift.ll23 ; CHECK: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 10
Ddo_switch3.s41 dsrl $2, $3, 32
/external/chromium_org/v8/test/cctest/
Dtest-disasm-mips64.cc432 COMPARE(dsrl(a0, a1, 0), in TEST()
434 COMPARE(dsrl(s0, s1, 8), in TEST()
436 COMPARE(dsrl(a6, a7, 24), in TEST()
438 COMPARE(dsrl(v0, v1, 31), in TEST()
/external/llvm/test/MC/Mips/mips1/
Dinvalid-mips3.s39 …dsrl $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
40 …dsrl $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
41 …dsrl $s3,$6,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
Dinvalid-mips4.s40 …dsrl $s3,$6,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
41 …dsrl $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
42 …dsrl $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
/external/llvm/test/MC/Disassembler/Mips/
Dmips64_le.txt38 # CHECK: dsrl $10, $gp, 24
Dmips64.txt41 # CHECK: dsrl $10, $gp, 24
Dmips64r2.txt38 # CHECK: dsrl $10, $gp, 24
Dmips64r2_le.txt38 # CHECK: dsrl $10, $gp, 24

12