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Searched refs:getLocReg (Results 1 – 17 of 17) sorted by relevance

/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp209 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), in LowerReturn_32()
214 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
296 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) { in LowerReturn_64()
304 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag); in LowerReturn_64()
308 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_64()
379 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi); in LowerFormalArguments_32()
394 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(), in LowerFormalArguments_32()
405 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments_32()
566 unsigned VReg = MF.addLiveIn(VA.getLocReg(), in LowerFormalArguments_64()
819 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Hi)); in LowerCall_32()
[all …]
/external/llvm/lib/Target/ARM/
DARMFastISel.cpp1983 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(Arg); in ProcessCallArgs()
1984 RegArgs.push_back(VA.getLocReg()); in ProcessCallArgs()
1996 TII.get(ARM::VMOVRRD), VA.getLocReg()) in ProcessCallArgs()
1997 .addReg(NextVA.getLocReg(), RegState::Define) in ProcessCallArgs()
1999 RegArgs.push_back(VA.getLocReg()); in ProcessCallArgs()
2000 RegArgs.push_back(NextVA.getLocReg()); in ProcessCallArgs()
2041 .addReg(RVLocs[0].getLocReg()) in FinishCall()
2042 .addReg(RVLocs[1].getLocReg())); in FinishCall()
2044 UsedRegs.push_back(RVLocs[0].getLocReg()); in FinishCall()
2045 UsedRegs.push_back(RVLocs[1].getLocReg()); in FinishCall()
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DARMISelLowering.cpp1281 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, in LowerCallResult()
1286 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, in LowerCallResult()
1300 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); in LowerCallResult()
1304 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); in LowerCallResult()
1314 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(), in LowerCallResult()
1360 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(id))); in PassF64ArgInRegs()
1363 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1-id))); in PassF64ArgInRegs()
1505 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
1964 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) in IsEligibleForTailCallOptimization()
2126 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
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/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp466 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
550 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
556 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
625 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCCCCallTo()
729 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), in LowerCallResult()
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp338 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); in LowerReturn()
342 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
383 RVLocs[i].getLocReg(), in LowerCallResult()
518 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
877 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
882 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
/external/llvm/lib/Target/AArch64/
DAArch64FastISel.cpp1247 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(Arg); in ProcessCallArgs()
1248 RegArgs.push_back(VA.getLocReg()); in ProcessCallArgs()
1298 ResultReg).addReg(RVLocs[0].getLocReg()); in FinishCall()
1299 UsedRegs.push_back(RVLocs[0].getLocReg()); in FinishCall()
1599 unsigned DestReg = VA.getLocReg(); in SelectRet()
1635 RetRegs.push_back(VA.getLocReg()); in SelectRet()
DAArch64ISelLowering.cpp1728 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments()
1941 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InFlag); in LowerCallResult()
2040 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) in isEligibleForTailCallOptimization()
2287 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
2520 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag); in LowerReturn()
2522 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/external/llvm/lib/Target/X86/
DX86FastISel.cpp1023 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) in X86SelectRet()
1052 unsigned DstReg = VA.getLocReg(); in X86SelectRet()
1061 RetRegs.push_back(VA.getLocReg()); in X86SelectRet()
2912 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(Arg); in DoSelectCall()
2913 RegArgs.push_back(VA.getLocReg()); in DoSelectCall()
3069 if ((RVLocs[i].getLocReg() == X86::ST0 || in DoSelectCall()
3070 RVLocs[i].getLocReg() == X86::ST1)) { in DoSelectCall()
3080 CopyReg).addReg(RVLocs[i].getLocReg()); in DoSelectCall()
3081 UsedRegs.push_back(RVLocs[i].getLocReg()); in DoSelectCall()
DX86ISelLowering.cpp1908 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) && in LowerReturn()
1921 if (VA.getLocReg() == X86::ST0 || in LowerReturn()
1922 VA.getLocReg() == X86::ST1) { in LowerReturn()
1936 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { in LowerReturn()
1948 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag); in LowerReturn()
1950 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
2067 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) { in LowerCallResult()
2083 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), in LowerCallResult()
2302 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments()
2726 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
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/external/llvm/include/llvm/CodeGen/
DCallingConvLower.h140 unsigned getLocReg() const { assert(isRegLoc()); return Loc; } in getLocReg() function
/external/llvm/lib/Target/XCore/
DXCoreISelLowering.cpp1072 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getValVT(), in LowerCallResult()
1169 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCCCCallTo()
1330 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
1520 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); in LowerReturn()
1525 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/external/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp1335 unsigned SourcePhysReg = VA.getLocReg(); in finishCall()
1548 unsigned RetReg = ValLocs[0].getLocReg(); in SelectRet()
1564 RetRegs.push_back(VA.getLocReg()); in SelectRet()
DPPCISelLowering.cpp2289 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments_32SVR4()
3535 VA.getLocReg(), VA.getLocVT(), InFlag); in LowerCallResult()
3867 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall_32SVR4()
4795 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag); in LowerReturn()
4797 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp2491 unsigned LocRegLo = VA.getLocReg(); in LowerCall()
2513 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
2623 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(), in LowerCallResult()
2697 unsigned ArgReg = VA.getLocReg(); in LowerFormalArguments()
2835 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag); in LowerReturn()
2839 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/external/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp717 MRI.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
795 unsigned Reg = VA.getLocReg(); in canUseSiblingCall()
858 RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue)); in LowerCall()
952 SDValue RetValue = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), in LowerCall()
998 unsigned Reg = VA.getLocReg(); in LowerReturn()
/external/llvm/lib/Target/R600/
DSIISelLowering.cpp413 unsigned Reg = VA.getLocReg(); in LowerFormalArguments()
438 Reg = ArgLocs[ArgIdx++].getLocReg(); in LowerFormalArguments()
DR600ISelLowering.cpp1683 unsigned Reg = MF.addLiveIn(VA.getLocReg(), &AMDGPU::R600_Reg128RegClass); in LowerFormalArguments()