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Searched refs:getRegClassFor (Results 1 – 22 of 22) sorted by relevance

/external/llvm/lib/CodeGen/SelectionDAG/
DResourcePriorityQueue.cpp100 && (TLI->getRegClassFor(VT)->getID() == RCId)) { in numberRCValPredInSU()
138 && (TLI->getRegClassFor(VT)->getID() == RCId)) { in numberRCValSuccInSU()
338 && TLI->getRegClassFor(VT) in rawRegPressureDelta()
339 && TLI->getRegClassFor(VT)->getID() == RCId) in rawRegPressureDelta()
349 if (TLI->isTypeLegal(VT) && TLI->getRegClassFor(VT) in rawRegPressureDelta()
350 && TLI->getRegClassFor(VT)->getID() == RCId) in rawRegPressureDelta()
491 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode()
502 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode()
DInstrEmitter.cpp108 UseRC = TLI->getRegClassFor(VT); in EmitCopyFromReg()
166 DstRC = TLI->getRegClassFor(VT); in EmitCopyFromReg()
228 TLI->getRegClassFor(Node->getSimpleValueType(i)); in CreateVirtualRegisters()
289 TLI->getRegClassFor(Op.getSimpleValueType()); in getVR()
452 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx); in ConstrainForSubReg()
487 TLI->getRegClassFor(Node->getSimpleValueType(0)); in EmitSubregNode()
542 const TargetRegisterClass *SRC = TLI->getRegClassFor(Node->getSimpleValueType(0)); in EmitSubregNode()
DFastISel.cpp235 Reg = createResultReg(TLI.getRegClassFor(VT)); in materializeRegForValue()
903 const TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT); in SelectBitCast()
904 const TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT); in SelectBitCast()
1587 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); in FastEmitInst_extractsubreg()
DFunctionLoweringInfo.cpp249 createVirtualRegister(TM.getTargetLowering()->getRegClassFor(VT)); in CreateReg()
DSelectionDAGISel.cpp910 const TargetRegisterClass *PtrRC = TLI->getRegClassFor(TLI->getPointerTy()); in PrepareEHLandingPad()
DSelectionDAGBuilder.cpp6548 if (const TargetRegisterClass *RC = TLI->getRegClassFor(RegVT)) in visitInlineAsm()
7514 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT)); in LowerArguments()
DDAGCombiner.cpp8337 const TargetRegisterClass *ResRC = TLI.getRegClassFor(ResVT.getSimpleVT()); in canMergeExpensiveCrossRegisterBankCopy()
8339 TLI.getRegClassFor(Use->getOperand(0).getValueType().getSimpleVT()); in canMergeExpensiveCrossRegisterBankCopy()
/external/llvm/lib/Target/ARM/
DARMFastISel.cpp448 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMoveToFPReg()
458 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMoveToIntReg()
484 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeFP()
500 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeFP()
537 unsigned ImmReg = createResultReg(TLI.getRegClassFor(MVT::i32)); in ARMMaterializeInt()
549 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeInt()
650 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeGV()
664 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeGV()
715 const TargetRegisterClass* RC = TLI.getRegClassFor(VT); in TargetMaterializeAlloca()
1023 RC = TLI.getRegClassFor(VT); in ARMEmitLoad()
[all …]
DARMISelLowering.h352 const TargetRegisterClass *getRegClassFor(MVT VT) const override;
DARMISelLowering.cpp1078 const TargetRegisterClass *ARMTargetLowering::getRegClassFor(MVT VT) const { in getRegClassFor() function in ARMTargetLowering
1088 return TargetLowering::getRegClassFor(VT); in getRegClassFor()
3905 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32)); in LowerRETURNADDR()
/external/llvm/lib/Target/AArch64/
DAArch64FastISel.cpp217 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in AArch64MaterializeFP()
235 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in AArch64MaterializeFP()
554 RC = TLI.getRegClassFor(VT); in EmitLoad()
559 RC = TLI.getRegClassFor(VT); in EmitLoad()
1074 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT)); in SelectSelect()
1188 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT)); in SelectIntToFP()
1295 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT)); in FinishCall()
1806 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT)); in EmitIntExt()
1874 unsigned QuotReg = createResultReg(TLI.getRegClassFor(DestVT)); in SelectRem()
1880 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT)); in SelectRem()
[all …]
/external/llvm/lib/Target/X86/
DX86FastISel.cpp1744 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86FastEmitCMoveSelect()
1922 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86FastEmitSSESelect()
1991 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86FastEmitPseudoSelect()
2019 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86SelectSelect()
2445 TLI.getRegClassFor(VT), RHSReg, RHSIsKill); in X86VisitIntrinsicCall()
2455 ResultReg = FastEmitInst_r(MULOpc[0], TLI.getRegClassFor(VT), RHSReg, in X86VisitIntrinsicCall()
2459 TLI.getRegClassFor(VT), LHSReg, LHSIsKill, in X86VisitIntrinsicCall()
2533 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in X86VisitIntrinsicCall()
2616 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); in FastLowerArguments()
3294 const TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy()); in TargetMaterializeAlloca()
DX86ISelLowering.cpp2348 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy)); in LowerFormalArguments()
9785 const TargetRegisterClass* rc = getRegClassFor(VecVT); in ExtractBitFromMaskVector()
9988 const TargetRegisterClass* rc = getRegClassFor(VecVT); in InsertBitToMaskVector()
13187 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32); in LowerDYNAMIC_STACKALLOC()
17078 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64); in EmitVAARG64WithCustomInserter()
17079 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32); in EmitVAARG64WithCustomInserter()
17514 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32); in EmitLoweredSegAlloca()
17785 const TargetRegisterClass *PtrRC = getRegClassFor(PVT); in emitEHSjLjSetJmp()
/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp961 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); in emitAtomicBinary()
1060 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); in emitSignExtendToI32InReg()
1080 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); in emitAtomicBinaryPartword()
1230 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); in emitAtomicCmpSwap()
1312 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); in emitAtomicCmpSwapPartword()
1892 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); in lowerRETURNADDR()
2698 const TargetRegisterClass *RC = getRegClassFor(RegVT); in LowerFormalArguments()
2765 getRegClassFor(Subtarget->isABI_N64() ? MVT::i64 : MVT::i32)); in LowerFormalArguments()
3039 RC = getRegClassFor(VT); in parseRegForInlineAsmConstraint()
3048 RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT); in parseRegForInlineAsmConstraint()
[all …]
DMipsSEISelDAGToDAG.cpp860 const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple); in selectNode()
/external/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp1339 const TargetRegisterClass *CpyRC = TLI.getRegClassFor(CopyVT); in finishCall()
1348 ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); in finishCall()
1822 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); in PPCMaterializeFP()
DPPCISelLowering.cpp6517 const TargetRegisterClass *PtrRC = getRegClassFor(PVT); in emitEHSjLjSetJmp()
/external/llvm/include/llvm/Target/
DTargetLowering.h314 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const { in getRegClassFor() function
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp987 unsigned Reg = MF.addLiveIn(TRI->getRARegister(), getRegClassFor(MVT::i32)); in LowerRETURNADDR()
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp567 getRegClassFor(VA.getLocVT())); in LowerFormalArguments_64()
2495 TLI.getRegClassFor(TLI.getPointerTy())); in LowerRETURNADDR()
/external/llvm/lib/Target/R600/
DSIISelLowering.cpp1311 return getRegClassFor(Op.getSimpleValueType()); in getRegClassForNode()
/external/llvm/lib/CodeGen/
DMachineScheduler.cpp2384 TLI->getRegClassFor(LegalIntVT)); in initPolicy()