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Searched refs:irq (Results 1 – 25 of 98) sorted by relevance

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/external/qemu/hw/arm/
Darm_gic.c52 #define GIC_SET_ENABLED(irq) s->irq_state[irq].enabled = 1 argument
53 #define GIC_CLEAR_ENABLED(irq) s->irq_state[irq].enabled = 0 argument
54 #define GIC_TEST_ENABLED(irq) s->irq_state[irq].enabled argument
55 #define GIC_SET_PENDING(irq, cm) s->irq_state[irq].pending |= (cm) argument
56 #define GIC_CLEAR_PENDING(irq, cm) s->irq_state[irq].pending &= ~(cm) argument
57 #define GIC_TEST_PENDING(irq, cm) ((s->irq_state[irq].pending & (cm)) != 0) argument
58 #define GIC_SET_ACTIVE(irq, cm) s->irq_state[irq].active |= (cm) argument
59 #define GIC_CLEAR_ACTIVE(irq, cm) s->irq_state[irq].active &= ~(cm) argument
60 #define GIC_TEST_ACTIVE(irq, cm) ((s->irq_state[irq].active & (cm)) != 0) argument
61 #define GIC_SET_MODEL(irq) s->irq_state[irq].model = 1 argument
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Darmv7m_nvic.c89 void armv7m_nvic_set_pending(void *opaque, int irq) in armv7m_nvic_set_pending() argument
92 if (irq >= 16) in armv7m_nvic_set_pending()
93 irq += 16; in armv7m_nvic_set_pending()
94 gic_set_pending_private(&s->gic, 0, irq); in armv7m_nvic_set_pending()
101 uint32_t irq; in armv7m_nvic_acknowledge_irq() local
103 irq = gic_acknowledge_irq(&s->gic, 0); in armv7m_nvic_acknowledge_irq()
104 if (irq == 1023) in armv7m_nvic_acknowledge_irq()
106 if (irq >= 32) in armv7m_nvic_acknowledge_irq()
107 irq -= 16; in armv7m_nvic_acknowledge_irq()
108 return irq; in armv7m_nvic_acknowledge_irq()
[all …]
Dpic.c25 static void arm_pic_cpu_handler(void *opaque, int irq, int level) in arm_pic_cpu_handler() argument
29 switch (irq) { in arm_pic_cpu_handler()
43 hw_error("arm_pic_cpu_handler: Bad interrput line %d\n", irq); in arm_pic_cpu_handler()
/external/qemu/hw/core/
Dirq.c33 void qemu_set_irq(qemu_irq irq, int level) in qemu_set_irq() argument
35 if (!irq) in qemu_set_irq()
38 irq->handler(irq->opaque, irq->n, level); in qemu_set_irq()
67 struct IRQState *irq = opaque; in qemu_notirq() local
69 irq->handler(irq->opaque, irq->n, !level); in qemu_notirq()
72 qemu_irq qemu_irq_invert(qemu_irq irq) in qemu_irq_invert() argument
75 qemu_irq_raise(irq); in qemu_irq_invert()
76 return qemu_allocate_irqs(qemu_notirq, irq, 1)[0]; in qemu_irq_invert()
Dsysbus.c26 void sysbus_connect_irq(SysBusDevice *dev, int n, qemu_irq irq) in sysbus_connect_irq() argument
31 *dev->irqp[n] = irq; in sysbus_connect_irq()
135 qemu_irq irq; in sysbus_create_varargs() local
147 irq = va_arg(va, qemu_irq); in sysbus_create_varargs()
148 if (!irq) { in sysbus_create_varargs()
151 sysbus_connect_irq(s, n, irq); in sysbus_create_varargs()
/external/qemu/hw/intc/
Di8259.c76 static inline void pic_set_irq1(PicState *s, int irq, int level) in pic_set_irq1() argument
79 mask = 1 << irq; in pic_set_irq1()
145 int irq2, irq; in pic_update_irq() local
155 irq = pic_get_irq(&s->pics[0]); in pic_update_irq()
156 if (irq >= 0) { in pic_update_irq()
184 static void i8259_set_irq(void *opaque, int irq, int level) in i8259_set_irq() argument
189 if (level != irq_level[irq]) { in i8259_set_irq()
191 printf("i8259_set_irq: irq=%d level=%d\n", irq, level); in i8259_set_irq()
193 irq_level[irq] = level; in i8259_set_irq()
196 irq_count[irq]++; in i8259_set_irq()
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/external/qemu/include/hw/
Dirq.h10 void qemu_set_irq(qemu_irq irq, int level);
12 static inline void qemu_irq_raise(qemu_irq irq) in qemu_irq_raise() argument
14 qemu_set_irq(irq, 1); in qemu_irq_raise()
17 static inline void qemu_irq_lower(qemu_irq irq) in qemu_irq_lower() argument
19 qemu_set_irq(irq, 0); in qemu_irq_lower()
22 static inline void qemu_irq_pulse(qemu_irq irq) in qemu_irq_pulse() argument
24 qemu_set_irq(irq, 1); in qemu_irq_pulse()
25 qemu_set_irq(irq, 0); in qemu_irq_pulse()
33 qemu_irq qemu_irq_invert(qemu_irq irq);
Ddevices.h27 void stellaris_gamepad_init(int n, qemu_irq *irq, const int *keycode);
45 void *retu_init(qemu_irq irq, int vilma);
46 void *tahvo_init(qemu_irq irq, int betty);
60 TC6393xbState *tc6393xb_init(uint32_t base, qemu_irq irq);
67 void sm501_init(uint32_t base, uint32_t local_mem_bytes, qemu_irq irq,
Dsysbus.h50 void sysbus_connect_irq(SysBusDevice *dev, int n, qemu_irq irq);
58 qemu_irq irq) in sysbus_create_simple() argument
60 return sysbus_create_varargs(name, addr, irq, NULL); in sysbus_create_simple()
/external/qemu/hw/android/goldfish/
Ddevice.c55 void goldfish_device_set_irq(struct goldfish_device *dev, int irq, int level) in goldfish_device_set_irq() argument
57 if(irq >= dev->irq_count) in goldfish_device_set_irq()
58 … cpu_abort (cpu_single_env, "goldfish_device_set_irq: Bad irq %d >= %d\n", irq, dev->irq_count); in goldfish_device_set_irq()
60 qemu_set_irq(goldfish_pic[dev->irq + irq], level); in goldfish_device_set_irq()
69 if(dev->irq == 0 && dev->irq_count > 0) { in goldfish_add_device_no_io()
70 dev->irq = goldfish_free_irq; in goldfish_add_device_no_io()
142 return s->current ? s->current->irq : 0; in goldfish_bus_read()
210 .irq = 1,
215 void goldfish_device_init(qemu_irq *pic, uint32_t base, uint32_t size, uint32_t irq, uint32_t irq_c… in goldfish_device_init() argument
219 goldfish_free_irq = irq; in goldfish_device_init()
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Devents_device.c56 qemu_irq irq; member
136 qemu_irq_raise(s->irq); in enqueue_event()
165 qemu_irq_lower(s->irq); in dequeue_event()
180 qemu_irq_lower(s->irq); in dequeue_event()
181 qemu_irq_raise(s->irq); in dequeue_event()
230 qemu_irq_raise(s->irq); in events_read()
353 void events_dev_init(uint32_t base, qemu_irq irq) in events_dev_init() argument
528 s->irq = irq; in events_dev_init()
Dtty.c209 int goldfish_tty_add(CharDriverState *cs, int id, uint32_t base, int irq) in goldfish_tty_add() argument
220 s->dev.irq = irq; in goldfish_tty_add()
/external/qemu/include/hw/i386/
Dpc.h12 SerialState *serial_init(int base, qemu_irq irq, int baudbase,
15 qemu_irq irq, int baudbase,
27 ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr);
28 ParallelState *parallel_mm_init(hwaddr base, int it_shift, qemu_irq irq, CharDriverState *chr);
34 void pic_set_irq(int irq, int level);
35 void pic_set_irq_new(void *opaque, int irq, int level);
66 PITState *pit_init(int base, qemu_irq irq);
94 RTCState *rtc_init(int base, qemu_irq irq, int base_year);
95 RTCState *rtc_init_sqw(int base, qemu_irq irq, qemu_irq sqw_irq, int base_year);
96 RTCState *rtc_mm_init(hwaddr base, int it_shift, qemu_irq irq,
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/external/qemu/hw/mips/
Dmips_int.c23 static void cpu_mips_irq_request(void *opaque, int irq, int level) in cpu_mips_irq_request() argument
27 if (irq < 0 || irq > 7) in cpu_mips_irq_request()
31 env->CP0_Cause |= 1 << (irq + CP0Ca_IP); in cpu_mips_irq_request()
33 env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP)); in cpu_mips_irq_request()
45 env->irq[i] = qi[i]; in cpu_mips_irq_init_cpu()
Dmips_pic.c17 static void mips_cpu_irq_handler(void *opaque, int irq, int level) in mips_cpu_irq_handler() argument
22 if (irq < 0 || 7 < irq) in mips_cpu_irq_handler()
24 irq); in mips_cpu_irq_handler()
26 causebit = 0x00000100 << irq; in mips_cpu_irq_handler()
/external/linux-tools-perf/perf-3.12.0/tools/perf/scripts/python/bin/
Dnetdev-times-record6 -e irq:irq_handler_entry -e irq:irq_handler_exit \
7 -e irq:softirq_entry -e irq:softirq_exit \
8 -e irq:softirq_raise $@
/external/qemu/include/hw/android/goldfish/
Ddevice.h27 uint32_t irq; // filled in by goldfish_device_add if 0 member
32 void goldfish_device_set_irq(struct goldfish_device *dev, int irq, int level);
40 void goldfish_device_init(qemu_irq *pic, uint32_t base, uint32_t size, uint32_t irq, uint32_t irq_c…
41 int goldfish_device_bus_init(uint32_t base, uint32_t irq);
46 int goldfish_tty_add(CharDriverState *cs, int id, uint32_t base, int irq);
57 void events_dev_init(uint32_t base, qemu_irq irq);
/external/qemu/include/hw/arm/
Dpxa.h86 qemu_irq irq);
88 qemu_irq irq);
94 qemu_irq irq);
101 BlockDriverState *bd, qemu_irq irq, void *dma);
110 void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq);
119 qemu_irq irq);
126 qemu_irq irq, uint32_t page_size);
192 qemu_irq irq; member
220 qemu_irq irq);
/external/qemu/hw/timer/
Dmc146818rtc.c70 qemu_irq irq; member
87 static void rtc_irq_raise(qemu_irq irq) { in rtc_irq_raise() argument
98 qemu_irq_raise(irq); in rtc_irq_raise()
125 rtc_irq_raise(s->irq); in rtc_coalesced_timer()
189 rtc_irq_raise(s->irq); in rtc_periodic_timer()
196 rtc_irq_raise(s->irq); in rtc_periodic_timer()
425 rtc_irq_raise(s->irq); in rtc_update_second2()
432 rtc_irq_raise(s->irq); in rtc_update_second2()
464 qemu_irq_lower(s->irq); in cmos_ioport_read()
589 qemu_irq_lower(s->irq); in rtc_reset()
[all …]
/external/qemu/include/hw/mips/
Dmips.h14 qemu_irq irq);
17 void mipsnet_init(int base, qemu_irq irq, NICInfo *nd);
39 qemu_irq irq, void* mem_opaque,
/external/qemu/include/hw/block/
Dfdc.h6 fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
9 fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, hwaddr io_base,
/external/kernel-headers/original/uapi/linux/
Db1lli.h48 int irq; member
58 int irq; member
Dserial.h22 int irq; member
79 int irq; member
/external/qemu/hw/android/
Dandroid_mips.c174 env->irq[2], env->irq[3]); in android_mips_init_()
199 smc91c111_init(&nd_table[i], smc_device->base, goldfish_pic[smc_device->irq]); in android_mips_init_()
220 events_dev_init(event0_device.base, goldfish_pic[event0_device.irq]); in android_mips_init_()
/external/linux-tools-perf/perf-3.12.0/tools/perf/scripts/python/
Dnetdev-times.py246 irq, irq_name):
248 irq, irq_name)
251 def irq__irq_handler_exit(name, context, cpu, sec, nsec, pid, comm, irq, ret): argument
252 event_info = (name, context, cpu, nsecs(sec, nsec), pid, comm, irq, ret)
302 (name, context, cpu, time, pid, comm, irq, irq_name) = event_info
305 irq_record = {'irq':irq, 'name':irq_name, 'cpu':cpu, 'irq_ent_t':time}
309 (name, context, cpu, time, pid, comm, irq, ret) = event_info
313 if irq != irq_record['irq']:

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