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Searched refs:is64BitVector (Results 1 – 6 of 6) sorted by relevance

/external/llvm/include/llvm/CodeGen/
DValueTypes.h131 bool is64BitVector() const { in is64BitVector() function
132 return isSimple() ? V.is64BitVector() : isExtended64BitVector(); in is64BitVector()
DMachineValueType.h203 bool is64BitVector() const { in is64BitVector() function
/external/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp275 SDValue GetVLDSTAlign(SDValue Align, unsigned NumVecs, bool is64BitVector);
1652 bool is64BitVector) { in GetVLDSTAlign() argument
1654 if (!is64BitVector && NumVecs < 3) in GetVLDSTAlign()
1786 bool is64BitVector = VT.is64BitVector(); in SelectVLD() local
1787 Align = GetVLDSTAlign(Align, NumVecs, is64BitVector); in SelectVLD()
1813 if (!is64BitVector) in SelectVLD()
1829 if (is64BitVector || NumVecs <= 2) { in SelectVLD()
1830 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : in SelectVLD()
1894 unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0); in SelectVLD()
1922 bool is64BitVector = VT.is64BitVector(); in SelectVST() local
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DARMISelLowering.cpp4117 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8; in getCTPOP16BitCounts()
4140 if (VT.is64BitVector()) { in lowerCTPOP16BitElements()
4174 EVT VT16Bit = VT.is64BitVector() ? MVT::v4i16 : MVT::v8i16; in lowerCTPOP32BitElements()
4182 if (VT.is64BitVector()) { in lowerCTPOP32BitElements()
4780 if (VT.is64BitVector() && EltSz == 32) in isVUZPMask()
4807 if (VT.is64BitVector() && EltSz == 32) in isVUZP_v_undef_Mask()
4829 if (VT.is64BitVector() && EltSz == 32) in isVZIPMask()
4854 if (VT.is64BitVector() && EltSz == 32) in isVZIP_v_undef_Mask()
5256 (VT.is128BitVector() || VT.is64BitVector())) { in isShuffleMaskLegal()
5857 assert(Op0.getValueType().is64BitVector() && in LowerMUL()
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/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp1720 else if (RegVT == MVT::f64 || RegVT.is64BitVector()) in LowerFormalArguments()
5694 (VT.is128BitVector() || VT.is64BitVector())) { in isShuffleMaskLegal()
6780 if (!NarrowTy.is64BitVector()) in tryExtendDUPToExtractHigh()
7001 assert(LHS.getValueType().is64BitVector() && in tryCombineLongOpWithDup()
7002 RHS.getValueType().is64BitVector() && in tryCombineLongOpWithDup()
DAArch64ISelDAGToDAG.cpp957 } else if (VT == MVT::f64 || VT.is64BitVector()) { in SelectIndexedLoad()