| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMMCCodeEmitter.cpp | 547 bool isAdd = true; in EncodeAddrModeOpValues() local
552 isAdd = false; in EncodeAddrModeOpValues()
558 isAdd = false; in EncodeAddrModeOpValues()
562 return isAdd; in EncodeAddrModeOpValues()
867 bool isAdd = true; in getAddrModeImm12OpValue() local
876 isAdd = false ; // 'U' bit is set as part of the fixup. in getAddrModeImm12OpValue()
891 isAdd = false; in getAddrModeImm12OpValue()
894 isAdd = false; in getAddrModeImm12OpValue()
899 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI); in getAddrModeImm12OpValue()
903 if (isAdd) in getAddrModeImm12OpValue()
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| D | ARMAsmBackend.cpp | 386 bool isAdd = true; in adjustFixupValue() local
389 isAdd = false; in adjustFixupValue()
393 Value |= isAdd << 23; in adjustFixupValue()
553 bool isAdd = true; in adjustFixupValue() local
556 isAdd = false; in adjustFixupValue()
562 return Value | (isAdd << 23); in adjustFixupValue()
571 bool isAdd = true; in adjustFixupValue() local
574 isAdd = false; in adjustFixupValue()
580 Value |= isAdd << 23; in adjustFixupValue()
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| /external/smali/dexlib2/src/main/java/org/jf/dexlib2/util/ |
| D | SyntheticAccessorFSM.java | 547 boolean isAdd = ((mathOp == ADD) && !negativeConstant) || in getIncrementType()
551 if (isAdd) { in getIncrementType()
557 if (isAdd) { in getIncrementType()
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| /external/smali/dexlib2/src/main/ragel/ |
| D | SyntheticAccessorFSM.rl | 245 boolean isAdd = ((mathOp == ADD) && !negativeConstant) ||
249 if (isAdd) {
255 if (isAdd) {
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| /external/valgrind/main/VEX/priv/ |
| D | host_arm64_defs.h | 636 Bool isAdd; member
1029 extern ARM64Instr* ARM64Instr_Arith ( HReg, HReg, ARM64RIA*, Bool isAdd );
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| D | host_arm64_defs.c | 1318 HReg argL, ARM64RIA* argR, Bool isAdd ) { in ARM64Instr_Arith() argument
1324 i->ARM64in.Arith.isAdd = isAdd; in ARM64Instr_Arith()
1939 vex_printf("%s ", i->ARM64in.Arith.isAdd ? "add" : "sub"); in ppARM64Instr()
4038 i->ARM64in.Arith.isAdd ? X10 : X11, in emit_ARM64Instr()
4047 i->ARM64in.Arith.isAdd ? X100 : X110, in emit_ARM64Instr()
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| D | host_ppc_defs.h | 600 Bool isAdd; /* else sub */ member
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| D | host_ppc_defs.c | 814 PPCInstr* PPCInstr_AddSubC ( Bool isAdd, Bool setC, in PPCInstr_AddSubC() argument
818 i->Pin.AddSubC.isAdd = isAdd; in PPCInstr_AddSubC()
1577 i->Pin.AddSubC.isAdd ? "add" : "sub", in ppPPCInstr()
3930 Bool isAdd = i->Pin.AddSubC.isAdd; in emit_PPCInstr() local
3936 if (isAdd) { in emit_PPCInstr()
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| D | guest_arm64_toIR.c | 2491 Bool isAdd = INSN(15,15) == 0; in dis_ARM64_data_processing_register() local
2498 binop(isAdd ? Iop_Add64 : Iop_Sub64, in dis_ARM64_data_processing_register()
2504 binop(isAdd ? Iop_Add32 : Iop_Sub32, in dis_ARM64_data_processing_register()
2509 isAdd ? "madd" : "msub", in dis_ARM64_data_processing_register()
2942 Bool isAdd = INSN(15,15) == 0; in dis_ARM64_data_processing_register() local
2956 assign(res, binop(isAdd ? Iop_Add64 : Iop_Sub64, in dis_ARM64_data_processing_register()
2959 DIP("%cm%sl %s, %s, %s, %s\n", isU ? 'u' : 's', isAdd ? "add" : "sub", in dis_ARM64_data_processing_register()
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| D | guest_amd64_toIR.c | 14758 static IRTemp math_HADDPS_128 ( IRTemp dV, IRTemp sV, Bool isAdd ) in math_HADDPS_128() argument
14774 assign( res, triop(isAdd ? Iop_Add32Fx4 : Iop_Sub32Fx4, in math_HADDPS_128()
14780 static IRTemp math_HADDPD_128 ( IRTemp dV, IRTemp sV, Bool isAdd ) in math_HADDPD_128() argument
14796 assign( res, triop(isAdd ? Iop_Add64Fx2 : Iop_Sub64Fx2, in math_HADDPD_128()
14854 Bool isAdd = opc == 0x7C; in dis_ESC_0F__SSE3() local
14855 const HChar* str = isAdd ? "add" : "sub"; in dis_ESC_0F__SSE3()
14871 putXMMReg( rG, mkexpr( math_HADDPS_128 ( gV, eV, isAdd ) ) ); in dis_ESC_0F__SSE3()
14879 Bool isAdd = opc == 0x7C; in dis_ESC_0F__SSE3() local
14880 const HChar* str = isAdd ? "add" : "sub"; in dis_ESC_0F__SSE3()
14896 putXMMReg( rG, mkexpr( math_HADDPD_128 ( gV, eV, isAdd ) ) ); in dis_ESC_0F__SSE3()
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| D | host_arm64_isel.c | 1687 Bool isAdd = e->Iex.Binop.op == Iop_Add64 in iselIntExpr_R_wrk() local
1692 addInstr(env, ARM64Instr_Arith(dst, argL, argR, isAdd)); in iselIntExpr_R_wrk()
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| D | guest_x86_toIR.c | 11934 Bool isAdd = insn[2] == 0x7C; in disInstr_X86_WRK() local
11935 const HChar* str = isAdd ? "add" : "sub"; in disInstr_X86_WRK()
11962 triop(isAdd ? Iop_Add32Fx4 : Iop_Sub32Fx4, in disInstr_X86_WRK()
11979 Bool isAdd = insn[1] == 0x7C; in disInstr_X86_WRK() local
11980 const HChar* str = isAdd ? "add" : "sub"; in disInstr_X86_WRK()
12008 triop(isAdd ? Iop_Add64Fx2 : Iop_Sub64Fx2, in disInstr_X86_WRK()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonHardwareLoops.cpp | 357 bool isAdd = (UpdOpc == Hexagon::ADD_ri); in findInductionRegister() local
359 if (isAdd) { in findInductionRegister()
1277 bool isAdd = (UpdOpc == Hexagon::ADD_ri); in fixupInductionVariable() local
1279 if (isAdd) { in fixupInductionVariable()
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 479 bool isAdd; member
2120 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0); in addAM3OffsetOperands()
2297 bool isAdd = Imm >= 0; in addPostIdxImm8Operands() local
2299 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8; in addPostIdxImm8Operands()
2308 bool isAdd = Imm >= 0; in addPostIdxImm8s4Operands() local
2311 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8; in addPostIdxImm8s4Operands()
2318 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd)); in addPostIdxRegOperands()
2326 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub; in addPostIdxRegShiftedOperands()
2693 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, in CreatePostIdxReg() argument
2697 Op->PostIdxReg.isAdd = isAdd; in CreatePostIdxReg()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMCodeEmitter.cpp | 300 bool isAdd = true; in getAddrMode5OpValue() local
303 isAdd = false; in getAddrMode5OpValue()
307 if (isAdd) in getAddrMode5OpValue()
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| D | ARMInstrInfo.td | 2474 // {12} isAdd
2492 // {12} isAdd
2584 // {12} isAdd
2603 // {12} isAdd
2620 // {12} isAdd
2639 // {12} isAdd
2737 // {12} isAdd
2755 // {12} isAdd
2897 // {12} isAdd
2916 // {12} isAdd
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| D | ARMInstrFormats.td | 653 // {12} isAdd
671 // {12} isAdd
692 // {12} isAdd
745 // {8} isAdd
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