| /external/llvm/include/llvm/MC/ |
| D | MCInstrDesc.h | 257 bool isBranch() const { in isBranch() function
272 return isBranch() & !isBarrier() & !isIndirectBranch(); in isConditionalBranch()
280 return isBranch() & isBarrier() & !isIndirectBranch(); in isUnconditionalBranch()
287 if (isBranch() || isCall() || isReturn() || isIndirectBranch()) in mayAffectControlFlow()
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| D | MCInstrAnalysis.h | 34 virtual bool isBranch(const MCInst &Inst) const { in isBranch() function
35 return Info->get(Inst.getOpcode()).isBranch(); in isBranch()
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| /external/llvm/lib/Target/X86/Disassembler/ |
| D | X86Disassembler.cpp | 205 static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch, in tryAddingSymbolicOperand() argument
209 return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch, in tryAddingSymbolicOperand()
295 bool isBranch = false; in translateImmediate() local
298 isBranch = true; in translateImmediate()
368 isBranch = true; in translateImmediate()
375 isBranch = true; in translateImmediate()
385 if(!tryAddingSymbolicOperand(immediate + pcrel, isBranch, insn.startLocation, in translateImmediate()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCHazardRecognizers.cpp | 61 if (!MCID->isBranch()) in isBCTRAfterSet()
178 if (CurSlots == 5 || (MCID->isBranch() && CurBranches == 1)) { in EmitInstruction()
199 if (MCID->isBranch()) in EmitInstruction()
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| D | PPCInstr64Bit.td | 84 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in {
106 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
251 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
257 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
263 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrTSX.td | 26 let isBranch = 1, isTerminator = 1, Defs = [EAX] in
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| D | X86InstrControl.td | 59 let isBarrier = 1, isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in {
71 let isBranch = 1, isTerminator = 1, Uses = [EFLAGS], SchedRW = [WriteJump] in {
103 let isBranch = 1, isTerminator = 1, hasSideEffects = 0, SchedRW = [WriteJump] in {
126 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430InstrInfo.cpp | 165 if (MI->isBranch() && !MI->isBarrier()) in isUnpredicatedTerminator()
192 if (!I->isBranch()) in AnalyzeBranch()
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineInstr.h | 429 bool isBranch(QueryType Type = AnyInBundle) const {
444 return isBranch(Type) & !isBarrier(Type) & !isIndirectBranch(Type);
452 return isBranch(Type) & isBarrier(Type) & !isIndirectBranch(Type);
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| /external/mesa3d/src/gallium/auxiliary/gallivm/ |
| D | lp_bld_debug.cpp | 359 if (TID.isBranch()) {
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.h | 119 bool isBranch(const MachineInstr *MI) const;
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| D | HexagonInstrInfo.cpp | 624 bool HexagonInstrInfo::isBranch (const MachineInstr *MI) const { in isBranch() function in HexagonInstrInfo
625 return MI->getDesc().isBranch(); in isBranch()
1507 if (isNewValue(MI) && isBranch(MI)) in isNewValueJump()
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| D | HexagonVLIWPacketizer.cpp | 1052 (MCIDJ.isBranch() || MCIDJ.isCall() || MCIDJ.isBarrier())) { in isLegalToPacketizeTogether()
1210 !MCIDJ.isBranch() && in isLegalToPacketizeTogether()
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| /external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/gallivm/ |
| D | lp_bld_debug.cpp | 359 if (TID.isBranch()) {
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| /external/llvm/lib/Target/Sparc/Disassembler/ |
| D | SparcDisassembler.cpp | 360 static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch, in tryAddingSymbolicOperand() argument
365 return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch, in tryAddingSymbolicOperand()
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| /external/llvm/lib/Target/ARM/ |
| D | Thumb2ITBlockPass.cpp | 204 (!MI->isBranch() && !MI->isReturn()) ; ++MBBI) { in InsertITInstructions()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenInstruction.h | 225 bool isBranch : 1; variable
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreInstrInfo.td | 622 let isBranch = 1, isTerminator = 1 in {
648 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
676 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1,
957 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
962 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
967 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
972 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
1106 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1,
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| /external/llvm/lib/MC/MCAnalysis/ |
| D | MCObjectDisassembler.cpp | 247 if (MIA.isBranch(LI.Inst)) { in buildCFG()
410 if (MIA.isBranch(TA->back().Inst)) { in getBBAt()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsDelaySlotFiller.cpp | 303 if (MI.isBranch()) { in init()
545 assert((!I->isCall() && !I->isReturn() && !I->isBranch()) && in searchRange()
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| D | MipsInstrInfo.td | 294 bit isBranch = 1;
682 let isBranch = 1;
694 let isBranch = 1;
730 let isBranch = 1;
747 let isBranch = 1;
789 let isBranch = 1;
1230 let isBranch = 1;
1391 let isBranch=1;
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| D | MipsCodeEmitter.cpp | 180 && MI.isBranch()) in getRelocation()
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| D | Mips16InstrInfo.td | 509 bit isBranch = 1;
515 bit isBranch = 1;
753 let isBranch=1;
765 let isBranch = 1;
773 let isBranch = 1;
780 let isBranch = 1;
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcInstrInfo.td | 578 let isBranch = 1;
588 let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in {
614 } // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1
618 let isTerminator = 1, isBarrier = 1, hasDelaySlot = 1, isBranch =1,
643 let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in {
668 } // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1
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| /external/llvm/lib/CodeGen/ |
| D | TwoAddressInstructionPass.cpp | 780 KillMI->isBranch() || KillMI->isTerminator()) in rescheduleMIBelowKill()
839 OtherMI->isBranch() || OtherMI->isTerminator()) in rescheduleMIBelowKill()
1018 OtherMI->isBranch() || OtherMI->isTerminator()) in rescheduleKillAboveMI()
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