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Searched refs:isCtrl (Results 1 – 9 of 9) sorted by relevance

/external/llvm/lib/CodeGen/SelectionDAG/
DResourcePriorityQueue.cpp76 if (I->isCtrl()) in numberRCValPredInSU()
114 if (I->isCtrl()) in numberRCValSuccInSU()
151 if (I->isCtrl()) in numberCtrlDepsInSU()
161 if (I->isCtrl()) in numberCtrlPredInSU()
280 if (I->isCtrl()) in isResourceAvailable()
513 if (I->isCtrl() || (I->getSUnit()->NumRegDefsLeft == 0)) in scheduledNode()
530 if (!I->isCtrl()) in scheduledNode()
DScheduleDAGRRList.cpp1025 if (I->isCtrl()) in CopyAndMoveSuccessors()
1034 if (I->isCtrl()) in CopyAndMoveSuccessors()
1067 && !D.isCtrl() && NewSU->NumRegDefsLeft > 0) in CopyAndMoveSuccessors()
1843 if (I->isCtrl()) continue; // ignore chain preds in CalcNodeSethiUllmanNumber()
1945 if (I->isCtrl()) in HighRegPressure()
1995 if (I->isCtrl()) in RegPressureDiff()
2039 if (I->isCtrl()) in scheduledNode()
2121 if (I->isCtrl()) in unscheduledNode()
2190 if (I->isCtrl()) continue; // ignore chain succs in closestSucc()
2209 if (I->isCtrl()) continue; // ignore chain preds in calcMaxScratches()
[all …]
DScheduleDAGSDNodes.cpp502 if (!SU->addPred(Dep) && !Dep.isCtrl() && OpSU->NumRegDefsLeft > 1) { in AddSchedEdges()
762 if (I->isCtrl()) continue; // ignore chain preds in EmitPhysRegCopy()
771 if (II->isCtrl()) continue; // ignore chain preds in EmitPhysRegCopy()
DScheduleDAGFast.cpp288 if (I->isCtrl()) in CopyAndMoveSuccessors()
298 if (I->isCtrl()) in CopyAndMoveSuccessors()
/external/llvm/include/llvm/CodeGen/
DScheduleDAG.h175 bool isCtrl() const { in isCtrl() function
653 return getSDep().isCtrl();
/external/llvm/lib/Target/PowerPC/
DPPCHazardRecognizers.cpp71 if (SU->Preds[i].isCtrl()) in isBCTRAfterSet()
/external/llvm/lib/Target/Hexagon/
DHexagonMachineScheduler.cpp72 if (I->isCtrl()) in isResourceAvailable()
/external/llvm/lib/CodeGen/
DScheduleDAGInstrs.cpp612 if (I->isCtrl()) in iterateChainSucc()
643 if (J->isCtrl()) in adjustChainDeps()
DMachineScheduler.cpp1305 if (PI->isCtrl()) { in apply()