Home
last modified time | relevance | path

Searched refs:isRegLoc (Results 1 – 16 of 16) sorted by relevance

/external/llvm/include/llvm/CodeGen/
DCallingConvLower.h135 bool isRegLoc() const { return !isMem; } in isRegLoc() function
140 unsigned getLocReg() const { assert(isRegLoc()); return Loc; } in getLocReg()
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp207 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn_32()
269 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn_64()
375 if (VA.isRegLoc()) { in LowerFormalArguments_32()
561 if (VA.isRegLoc()) { in LowerFormalArguments_64()
818 if (VA.isRegLoc()) { in LowerCall_32()
822 if (NextVA.isRegLoc()) { in LowerCall_32()
855 if (VA.isRegLoc()) { in LowerCall_32()
1013 if (!VA.isRegLoc() || (ValTy != MVT::f64 && ValTy != MVT::f128)) in fixupVariableFloatArgs()
1125 if (VA.isRegLoc()) { in LowerCall_64()
1165 if (i+1 < ArgLocs.size() && ArgLocs[i+1].isRegLoc() && in LowerCall_64()
/external/llvm/lib/Target/ARM/
DARMFastISel.cpp1901 if (VA.isRegLoc() && !VA.needsCustom()) { in ProcessCallArgs()
1907 !VA.isRegLoc() || !ArgLocs[++i].isRegLoc()) in ProcessCallArgs()
1981 if (VA.isRegLoc() && !VA.needsCustom()) { in ProcessCallArgs()
1992 assert(VA.isRegLoc() && NextVA.isRegLoc() && in ProcessCallArgs()
2109 if (!VA.isRegLoc()) in SelectRet()
DARMISelLowering.cpp1362 if (NextVA.isRegLoc()) in PassF64ArgInRegs()
1484 if (VA.isRegLoc()) { in LowerCall()
1497 } else if (VA.isRegLoc()) { in LowerCall()
1959 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) in IsEligibleForTailCallOptimization()
1963 if (RVLocs1[i].isRegLoc()) { in IsEligibleForTailCallOptimization()
2013 if (!VA.isRegLoc()) in IsEligibleForTailCallOptimization()
2015 if (!ArgLocs[++i].isRegLoc()) in IsEligibleForTailCallOptimization()
2018 if (!ArgLocs[++i].isRegLoc()) in IsEligibleForTailCallOptimization()
2020 if (!ArgLocs[++i].isRegLoc()) in IsEligibleForTailCallOptimization()
2023 } else if (!VA.isRegLoc()) { in IsEligibleForTailCallOptimization()
[all …]
/external/llvm/lib/Target/XCore/
DXCoreISelLowering.cpp1071 if (VA.isRegLoc()) { in LowerCallResult()
1168 if (VA.isRegLoc()) { in LowerCCCCallTo()
1316 if (VA.isRegLoc()) { in LowerCCCArguments()
1489 if (VA.isRegLoc()) in LowerReturn()
1517 if (!VA.isRegLoc()) in LowerReturn()
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp517 if (VA.isRegLoc()) { in LowerCall()
867 if ( (VA.isRegLoc() && !Flags.isByVal()) in LowerFormalArguments()
868 || (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() > 8)) { in LowerFormalArguments()
887 } else if (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() <= 8) { in LowerFormalArguments()
/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp452 if (VA.isRegLoc()) { in LowerCCCArguments()
548 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
624 if (VA.isRegLoc()) { in LowerCCCCallTo()
/external/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp1219 !VA.isRegLoc() || VA.needsCustom()) in processCallArgs()
1325 assert(VA.isRegLoc() && "Can only return in registers!"); in finishCall()
1563 assert(VA.isRegLoc() && "Can only return in registers!"); in SelectRet()
DPPCISelLowering.cpp2256 if (VA.isRegLoc()) { in LowerFormalArguments_32SVR4()
3532 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerCallResult()
3861 if (VA.isRegLoc()) { in LowerCall_32SVR4()
4777 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
/external/llvm/lib/Target/AArch64/
DAArch64FastISel.cpp1245 if (VA.isRegLoc() && !VA.needsCustom()) { in ProcessCallArgs()
1592 if (!VA.isRegLoc()) in SelectRet()
DAArch64ISelLowering.cpp1707 if (VA.isRegLoc()) { in LowerFormalArguments()
2015 if (!ArgLocs[i].isRegLoc()) in isEligibleForTailCallOptimization()
2035 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) in isEligibleForTailCallOptimization()
2039 if (RVLocs1[i].isRegLoc()) { in isEligibleForTailCallOptimization()
2279 if (VA.isRegLoc()) { in LowerCall()
2500 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
/external/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp691 if (VA.isRegLoc()) { in LowerFormalArguments()
793 if (!VA.isRegLoc()) in canUseSiblingCall()
856 if (VA.isRegLoc()) in LowerCall()
992 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp2479 if (VA.isRegLoc()) { in LowerCall()
2512 if (VA.isRegLoc()) { in LowerCall()
2682 bool IsRegLoc = VA.isRegLoc(); in LowerFormalArguments()
2830 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
/external/llvm/lib/Target/X86/
DX86FastISel.cpp1018 if (!VA.isRegLoc()) in X86SelectRet()
2910 if (VA.isRegLoc()) { in DoSelectCall()
DX86ISelLowering.cpp1888 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
2274 if (VA.isRegLoc()) { in LowerFormalArguments()
2725 if (VA.isRegLoc()) { in LowerCall()
2817 if (VA.isRegLoc()) in LowerCall()
3215 if (!ArgLocs[i].isRegLoc()) in IsEligibleForTailCallOptimization()
3257 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) in IsEligibleForTailCallOptimization()
3261 if (RVLocs1[i].isRegLoc()) { in IsEligibleForTailCallOptimization()
3302 if (!VA.isRegLoc()) { in IsEligibleForTailCallOptimization()
3327 if (!VA.isRegLoc()) in IsEligibleForTailCallOptimization()
/external/llvm/lib/Target/R600/
DSIISelLowering.cpp411 assert(VA.isRegLoc() && "Parameter must be in a register!"); in LowerFormalArguments()