| /external/llvm/lib/Target/ARM/ |
| D | ARMSelectionDAGInfo.cpp | 173 Entry.isSExt = false; in EmitTargetCodeForMemset()
185 Entry.isSExt = true; in EmitTargetCodeForMemset()
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| D | ARMFastISel.cpp | 2126 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) { in SelectRet()
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| D | ARMISelLowering.cpp | 6104 Entry.isSExt = false; in LowerFSINCOS()
6111 Entry.isSExt = false; in LowerFSINCOS()
10578 Entry.isSExt = isSigned; in LowerDivRem()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 1076 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD; in Select() local
1079 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); in Select()
1085 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break; in Select()
1091 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); in Select()
1096 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break; in Select()
1110 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD; in Select() local
1113 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); in Select()
1119 case MVT::i16: Opcode = isSExt ? PPC::LHAUX : PPC::LHZUX; break; in Select()
1125 assert((!isSExt || LoadedVT == MVT::i16 || LoadedVT == MVT::i32) && in Select()
1130 case MVT::i32: Opcode = isSExt ? PPC::LWAUX : PPC::LWZUX8; break; in Select()
[all …]
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| D | PPCISelLowering.cpp | 2420 if (Flags.isSExt()) in extendArgForPPC64()
4080 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerCall_64SVR4()
4509 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerCall_Darwin()
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| /external/llvm/include/llvm/Target/ |
| D | TargetCallingConv.h | 66 bool isSExt() const { return Flags & SExt; } in isSExt() function
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| D | TargetLowering.h | 2110 bool isSExt : 1; member
2120 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false), in ArgListEntry()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZCallingConv.td | 13 : CCIf<"ArgFlags.isSExt() || ArgFlags.isZExt()", A>;
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.cpp | 723 bool isSExt = true; in getCopyFromRegs() local
726 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 in getCopyFromRegs()
728 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 in getCopyFromRegs()
730 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 in getCopyFromRegs()
732 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 in getCopyFromRegs()
734 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 in getCopyFromRegs()
736 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 in getCopyFromRegs()
738 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 in getCopyFromRegs()
740 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 in getCopyFromRegs()
746 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, in getCopyFromRegs()
[all …]
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| D | LegalizeDAG.cpp | 2039 Entry.isSExt = isSigned; in ExpandLibCall()
2087 Entry.isSExt = isSigned; in ExpandLibCall()
2121 Entry.isSExt = isSigned; in ExpandChainLibCall()
2250 Entry.isSExt = isSigned; in ExpandDivRemLibCall()
2259 Entry.isSExt = isSigned; in ExpandDivRemLibCall()
2357 Entry.isSExt = false; in ExpandSinCosLibCall()
2365 Entry.isSExt = false; in ExpandSinCosLibCall()
2373 Entry.isSExt = false; in ExpandSinCosLibCall()
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| D | LegalizeTypes.cpp | 1046 Entry.isSExt = isSigned; in ExpandChainLibCall()
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| D | TargetLowering.cpp | 72 isSExt = CS->paramHasAttr(AttrIdx, Attribute::SExt); in setAttributes()
99 Entry.isSExt = isSigned; in makeLibCall()
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| D | LegalizeIntegerTypes.cpp | 2334 Entry.isSExt = true; in ExpandIntRes_XMULO()
2342 Entry.isSExt = true; in ExpandIntRes_XMULO()
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| D | SelectionDAG.cpp | 4348 Entry.isSExt = true; in getMemset()
4352 Entry.isSExt = false; in getMemset()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 123 if (ArgFlags.isSExt()) in CC_Hexagon_VarArg()
161 if (ArgFlags.isSExt()) in CC_Hexagon()
236 if (ArgFlags.isSExt()) in RetCC_Hexagon()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 895 if (Outs[OIdx].Flags.isSExt()) in LowerCall()
906 else if (Outs[OIdx].Flags.isSExt()) in LowerCall()
1745 ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ? in LowerFormalArguments()
1878 ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ? in LowerFormalArguments()
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| /external/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 1034 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt()) in X86SelectRet()
1040 if (Outs[0].Flags.isSExt()) in X86SelectRet()
2782 if (Flags.isSExt()) in DoSelectCall()
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| D | X86ISelLowering.cpp | 15131 Entry.isSExt = false; in LowerWin64_i128OP()
16131 Entry.isSExt = false; in LowerFSINCOS()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 310 if (ArgFlags.isSExt()) in AnalyzeArguments()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 1621 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt()) in SelectRet()
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| D | AArch64ISelLowering.cpp | 1499 Entry.isSExt = false; in LowerFSINCOS()
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| /external/llvm/lib/Target/R600/ |
| D | SIISelLowering.cpp | 407 Ins[i].Flags.isSExt()); in LowerFormalArguments()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 2226 if (ArgFlags.isSExt()) in CC_MipsO32()
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