| /external/llvm/test/CodeGen/Mips/ |
| D | o32_cc.ll | 146 ; FP64EL-DAG: mfhc1 $7, $f{{[0-9]+}}
163 ; FP64EL-DAG: mfhc1 $7, $f{{[0-9]+}}
223 ; FP64EL-DAG: mfhc1 $7, $f{{[0-9]+}}
285 ; FP64EL-DAG: mfhc1 $7, $f{{[0-9]+}}
315 ; FP64EL-DAG: mfhc1 $7, $f{{[0-9]+}}
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| D | buildpairextractelementf64.ll | 25 ; FP64-DAG: mfhc1
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| D | mno-ldc1-sdc1.ll | 131 ; 32R6-LE-PIC-DAG: mfhc1 $[[R1:[0-9]+]], $f12
150 ; 32R6-LE-STATIC-DAG: mfhc1 $[[R1:[0-9]+]], $f12
167 ; 32R6-BE-PIC-DAG: mfhc1 $[[R1:[0-9]+]], $f12
233 ; 32R6-DAG: mfhc1 $[[R1:[0-9]+]], $f12
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| /external/llvm/test/MC/Mips/mips64/ |
| D | invalid-mips64r2.s | 18 …mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
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| /external/llvm/test/MC/Mips/ |
| D | mips-fpu-instructions.s | 172 # CHECK: mfhc1 $17, $f4 # encoding: [0x00,0x20,0x71,0x44]
207 mfhc1 $17, $f4
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| /external/llvm/test/MC/Mips/mips32/ |
| D | invalid-mips32r2.s | 17 …mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
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| /external/llvm/test/MC/Mips/mips4/ |
| D | invalid-mips64r2.s | 24 …mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
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| /external/llvm/test/MC/Mips/mips5/ |
| D | invalid-mips64r2.s | 28 …mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
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| /external/llvm/test/MC/Mips/mips32r2/ |
| D | valid.s | 84 mfhc1 $s8,$f24
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| /external/llvm/lib/Target/Mips/ |
| D | MicroMipsInstrFPU.td | 126 def MFHC1_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, FGRH32Opnd, II_MFHC1>,
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| D | MipsInstrFPU.td | 365 def MFHC1 : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, FGRH32Opnd, II_MFHC1>,
|
| /external/chromium_org/v8/test/cctest/ |
| D | test-assembler-mips64.cc | 373 __ mfhc1(a5, f4); in TEST() local
386 __ mfhc1(a4, f4); in TEST() local
793 __ mfhc1(a5, f0); in TEST() local
800 __ mfhc1(a5, f0); // f0 MS 32 bits of long. in TEST() local
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| D | test-assembler-mips.cc | 367 __ mfhc1(t1, f4); in TEST() local
369 __ mfhc1(t3, f6); in TEST() local
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| /external/llvm/test/MC/Mips/mips2/ |
| D | invalid-mips32r2.s | 28 …mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
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| /external/llvm/test/MC/Mips/mips64r2/ |
| D | valid.s | 143 mfhc1 $s8,$f24
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| /external/chromium_org/v8/src/mips64/ |
| D | macro-assembler-mips64.h | 258 mfhc1(dst_high, src); in Move()
262 mfhc1(dst_high, src); in FmoveHigh()
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| D | lithium-codegen-mips64.cc | 3751 __ mfhc1(scratch1, input); // Get exponent/sign bits. in DoMathFloor() local
3767 __ mfhc1(result, input); in DoMathRound() local
3796 __ mfhc1(result, double_scratch0()); in DoMathRound() local
3828 __ mfhc1(scratch, input); // Get exponent/sign bits. in DoMathRound() local
4885 __ mfhc1(scratch, result_reg); // Get exponent/sign bits. in EmitNumberUntagD() local
4982 __ mfhc1(scratch1, double_scratch); // Get exponent/sign bits. in DoDeferredTaggedToI() local
5066 __ mfhc1(scratch1, double_input); // Get exponent/sign bits. in DoDoubleToI() local
5099 __ mfhc1(scratch1, double_input); // Get exponent/sign bits. in DoDoubleToSmi() local
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| D | assembler-mips64.h | 900 void mfhc1(Register rt, FPURegister fs);
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| D | assembler-mips64.cc | 2246 void Assembler::mfhc1(Register rt, FPURegister fs) { in mfhc1() function in v8::internal::Assembler
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| /external/chromium_org/v8/src/mips/ |
| D | assembler-mips.h | 869 void mfhc1(Register rt, FPURegister fs);
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| D | assembler-mips.cc | 1996 mfhc1(at, fd); in sdc1()
2025 void Assembler::mfhc1(Register rt, FPURegister fs) { in mfhc1() function in v8::internal::Assembler
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| D | macro-assembler-mips.cc | 1334 mfhc1(rt, fs); in Mfhc1()
|