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Searched refs:movn (Results 1 – 25 of 82) sorted by relevance

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/external/llvm/test/MC/AArch64/
Dtls-relocs.s7 movn x2, #:dtprel_g2:var
9 movn x4, #:dtprel_g2:var
29 movn x6, #:dtprel_g1:var
31 movn w8, #:dtprel_g1:var
61 movn x12, #:dtprel_g0:var
63 movn w14, #:dtprel_g0:var
219 movn x4, #:tprel_g2:var
231 movn x6, #:tprel_g1:var
233 movn w8, #:tprel_g1:var
263 movn x12, #:tprel_g0:var
[all …]
Darm64-tls-relocs.s44 movn x4, #:tprel_g2:var
55 movn x6, #:tprel_g1:var
81 movn x12, #:tprel_g0:var
168 movn x4, #:dtprel_g2:var
179 movn x6, #:dtprel_g1:var
205 movn x12, #:dtprel_g0:var
Delf-reloc-movw.s17 movn x17, #:abs_g0_s:some_label
20 movn x19, #:abs_g1_s:some_label
23 movn x19, #:abs_g2_s:some_label
/external/valgrind/main/none/tests/mips32/
DMoveIns.stdout.exp-BE193 movn.s $f0, $f2, $t3 :: fs rt 0x0
194 movn.s $f0, $f2, $t3 :: fs rt 0x43e41fde
195 movn.s $f0, $f2, $t3 :: fs rt 0x40400000
196 movn.s $f0, $f2, $t3 :: fs rt 0xbf800000
197 movn.s $f0, $f2, $t3 :: fs rt 0x44ad1333
198 movn.s $f0, $f2, $t3 :: fs rt 0x0
199 movn.s $f0, $f2, $t3 :: fs rt 0x0
200 movn.s $f0, $f2, $t3 :: fs rt 0xc5b4d3c3
201 movn.s $f0, $f2, $t3 :: fs rt 0x44db0000
202 movn.s $f0, $f2, $t3 :: fs rt 0x3b210e02
[all …]
/external/llvm/test/MC/Mips/
Dmicromips-movcond-instructions.s13 # CHECK-EL: movn $9, $6, $7 # encoding: [0xe6,0x00,0x18,0x48]
20 # CHECK-EB: movn $9, $6, $7 # encoding: [0x00,0xe6,0x48,0x18]
24 movn $9, $6, $7
Dmicromips-fpu-instructions.s58 # CHECK-EL: movn.s $f4, $f6, $7 # encoding: [0xe6,0x54,0x38,0x20]
59 # CHECK-EL: movn.d $f4, $f6, $7 # encoding: [0xe6,0x54,0x38,0x21]
121 # CHECK-EB: movn.s $f4, $f6, $7 # encoding: [0x54,0xe6,0x20,0x38]
122 # CHECK-EB: movn.d $f4, $f6, $7 # encoding: [0x54,0xe6,0x21,0x38]
180 movn.s $f4, $f6, $7
181 movn.d $f4, $f6, $7
/external/llvm/test/CodeGen/Mips/
Dzeroreg.ll16 ; 32-CMOV: movn $2, $zero, $4
22 ; 64-CMOV: movn $2, $zero, $4
63 ; 32-CMOV-DAG: movn $[[R0]], $zero, $4
64 ; 32-CMOV-DAG: movn $[[R1]], $zero, $4
73 ; 64-CMOV: movn $2, $zero, $4
Dcmov.ll16 ; 32-CMOV-DAG: movn $[[R0]], $[[R1]], $4
28 ; 64-CMOV-DAG: movn $[[R0]], $[[R1]], $4
56 ; 32-CMOV-DAG: movn $[[R1]], $[[R0]], $4
68 ; 64-CMOV: movn $[[R1]], $[[R0]], $4
205 ; 32-CMOV-DAG: movn $[[I5]], $[[I7]], $[[R0]]
220 ; 64-CMOV-DAG: movn $[[I5]], $[[I7]], $[[R0]]
280 ; 32-CMOV-DAG: movn $[[I5]], $[[I3]], $[[R0]]
297 ; 64-CMOV-DAG: movn $[[I5]], $[[I3]], $[[R0]]
326 ; 32-CMOV-DAG: movn $[[I4]], $[[I5]], $[[CC]]
371 ; 32-CMOV-DAG: movn $[[I4]], $[[I5]], $[[CC]]
[all …]
Dselect.ll15 ; 32: movn $5, $6, $4
18 ; 32R2: movn $5, $6, $4
25 ; 64: movn $5, $6, $4
28 ; 64R2: movn $5, $6, $4
45 ; 32-DAG: movn $6, $[[F1]], $4
47 ; 32: movn $7, $[[F1H]], $4
52 ; 32R2-DAG: movn $6, $[[F1]], $4
54 ; 32R2: movn $7, $[[F1H]], $4
67 ; 64: movn $5, $6, $4
70 ; 64R2: movn $5, $6, $4
[all …]
/external/llvm/test/CodeGen/AArch64/
Dmovw-consts.ll56 ; CHECK: movn w0, #{{60875|0xedcb}}
62 ; CHECK: movn x0, #0
68 ; CHECK: movn x0, #{{60875|0xedcb}}, lsl #16
113 ; CHECK: movn {{w[0-9]+}}, #0
Darm64-movi.ll79 define i64 @movn() nounwind {
80 ; CHECK-LABEL: movn:
81 ; CHECK: movn x0, #0x29
87 ; CHECK: movn x0, #0x29, lsl #32
Darm64-variadic-aapcs.ll35 ; CHECK: movn [[GR_OFFS:w[0-9]+]], #0x37
73 ; CHECK: movn [[GR_OFFS:w[0-9]+]], #0x27
76 ; CHECK: movn [[VR_OFFS:w[0-9]+]], #0x6f
Darm64-icmp-opt.ll11 ; CHECK-NOT: movn
/external/llvm/lib/Target/Mips/
DMipsCondMov.td118 def MOVN_I_I : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd, II_MOVN>,
122 def MOVN_I_I64 : CMov_I_I_FT<"movn", GPR32Opnd, GPR64Opnd, II_MOVN>,
124 def MOVN_I64_I : CMov_I_I_FT<"movn", GPR64Opnd, GPR32Opnd, II_MOVN>,
126 def MOVN_I64_I64 : CMov_I_I_FT<"movn", GPR64Opnd, GPR64Opnd, II_MOVN>,
138 def MOVN_I_S : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd, II_MOVN_S>,
142 def MOVN_I64_S : CMov_I_F_FT<"movn.s", GPR64Opnd, FGR32Opnd, II_MOVN_S>,
149 def MOVN_I_D32 : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd,
156 def MOVN_I_D64 : CMov_I_F_FT<"movn.d", GPR32Opnd, FGR64Opnd, II_MOVN_D>,
161 def MOVN_I64_D64 : CMov_I_F_FT<"movn.d", GPR64Opnd, FGR64Opnd, II_MOVN_D>,
/external/llvm/test/MC/Mips/mips32r6/
Dinvalid-mips32.s15 …movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
16 …movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
17 …movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/external/libhevc/common/arm64/
Dihevc_sao_edge_offset_class2_chroma.s142 movn x20,#0
150 movn x20,#0
178 movn x20,#0
185 movn x20,#0
224 movn x20,#0
234 movn x20,#0
260 movn x20,#0
270 movn x20,#0
427 movn x20,#0
434 movn x20,#0
[all …]
Dihevc_sao_edge_offset_class3_chroma.s137 movn x20,#0
146 movn x20,#0
170 movn x20,#0
179 movn x20,#0
216 movn x20,#0
225 movn x20,#0
251 movn x20,#0
260 movn x20,#0
411 movn x20,#0
419 movn x20,#0
[all …]
Dihevc_sao_edge_offset_class2.s125 movn x20,#0
134 movn x20,#0
169 movn x20,#0
175 movn x20,#0
306 movn x20,#0
380 movn x20,#0
394 movn x20,#0
484 movn x20,#0
625 movn x20,#0
758 movn x20,#0
Dihevc_sao_edge_offset_class3.s130 movn x20,#0
137 movn x20,#0
176 movn x20,#0
182 movn x20,#0
319 movn x20,#0
383 movn x20,#0
413 movn x20,#0
514 movn x20,#0
663 movn x20,#0
803 movn x20,#0
/external/llvm/test/MC/Mips/mips3/
Dinvalid-mips4.s18 …movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
19 …movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
20 …movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
Dinvalid-mips5.s19 …movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
20 …movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
21 …movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
/external/llvm/test/MC/Mips/mips2/
Dinvalid-mips32.s28 …movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
29 …movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
30 …movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
/external/chromium_org/v8/test/cctest/
Dtest-disasm-mips.cc467 COMPARE(movn(a0, a1, a2), in TEST()
469 COMPARE(movn(s0, s1, s2), in TEST()
471 COMPARE(movn(t2, t3, t4), in TEST()
473 COMPARE(movn(v0, v1, a2), in TEST()
/external/llvm/test/MC/Mips/mips32/
Dvalid.s82 movn $v1,$s1,$s0
83 movn.d $f27,$f21,$k0
84 movn.s $f12,$f0,$s7
/external/llvm/test/MC/Mips/mips64r6/
Dinvalid-mips64.s29 …movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
30 …movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
31 …movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…

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