| /external/llvm/test/MC/AArch64/ |
| D | trace-regs.s | 3 mrs x8, trcstatr
4 mrs x9, trcidr8
5 mrs x11, trcidr9
6 mrs x25, trcidr10
7 mrs x7, trcidr11
8 mrs x7, trcidr12
9 mrs x6, trcidr13
10 mrs x27, trcidr0
11 mrs x29, trcidr1
12 mrs x4, trcidr2
[all …]
|
| D | arm64-system-encoding.s | 217 mrs x3, ACTLR_EL1
218 mrs x3, ACTLR_EL2
219 mrs x3, ACTLR_EL3
220 mrs x3, AFSR0_EL1
221 mrs x3, AFSR0_EL2
222 mrs x3, AFSR0_EL3
223 mrs x3, AIDR_EL1
224 mrs x3, AFSR1_EL1
225 mrs x3, AFSR1_EL2
226 mrs x3, AFSR1_EL3
[all …]
|
| D | gicv3-regs.s | 3 mrs x8, icc_iar1_el1
4 mrs x26, icc_iar0_el1
5 mrs x2, icc_hppir1_el1
6 mrs x17, icc_hppir0_el1
7 mrs x29, icc_rpr_el1
8 mrs x4, ich_vtr_el2
9 mrs x24, ich_eisr_el2
10 mrs x9, ich_elsr_el2
11 mrs x24, icc_bpr1_el1
12 mrs x14, icc_bpr0_el1
[all …]
|
| D | basic-a64-instructions.s | 4186 mrs x9, TEECR32_EL1
4187 mrs x9, OSDTRRX_EL1
4188 mrs x9, MDCCSR_EL0
4189 mrs x9, MDCCINT_EL1
4190 mrs x9, MDSCR_EL1
4191 mrs x9, OSDTRTX_EL1
4192 mrs x9, DBGDTR_EL0
4193 mrs x9, DBGDTRRX_EL0
4194 mrs x9, OSECCR_EL1
4195 mrs x9, DBGVCR32_EL2
[all …]
|
| D | gicv3-regs-diagnostics.s | 4 mrs x10, icc_eoir1_el1
5 mrs x7, icc_eoir0_el1
6 mrs x22, icc_dir_el1
7 mrs x24, icc_sgi1r_el1
8 mrs x8, icc_asgi1r_el1
9 mrs x28, icc_sgi0r_el1
|
| D | arm64-spsel-sysreg.s | 8 mrs x0, SPSel label
9 mrs x0, ESR_EL1 label
21 mrs x0, DAIFSet label
|
| D | trace-regs-diagnostics.s | 3 mrs x12, trcoslar
4 mrs x10, trclar
|
| D | basic-a64-diagnostics.s | 3660 mrs x9, DBGDTRTX_EL0
3661 mrs x9, OSLAR_EL1
3662 mrs x9, PMSWINC_EL0
3663 mrs x9, PMEVCNTR31_EL0
3664 mrs x9, PMEVTYPER31_EL0
3682 mrs xzr, s2_5_c11_c13_2
3683 mrs x12, s3_8_c11_c13_2
3684 mrs x13, s3_3_c12_c13_2
3685 mrs x19, s3_2_c15_c16_2
3686 mrs x30, s3_2_c15_c1_8
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | trace-regs.txt | 5 # CHECK: mrs x8, {{trcstatr|TRCSTATR}}
7 # CHECK: mrs x9, {{trcidr8|TRCIDR8}}
9 # CHECK: mrs x11, {{trcidr9|TRCIDR9}}
11 # CHECK: mrs x25, {{trcidr10|TRCIDR10}}
13 # CHECK: mrs x7, {{trcidr11|TRCIDR11}}
15 # CHECK: mrs x7, {{trcidr12|TRCIDR12}}
17 # CHECK: mrs x6, {{trcidr13|TRCIDR13}}
19 # CHECK: mrs x27, {{trcidr0|TRCIDR0}}
21 # CHECK: mrs x29, {{trcidr1|TRCIDR1}}
23 # CHECK: mrs x4, {{trcidr2|TRCIDR2}}
[all …]
|
| D | gicv3-regs.txt | 5 # CHECK: mrs x8, {{icc_iar1_el1|ICC_IAR1_EL1}}
7 # CHECK: mrs x26, {{icc_iar0_el1|ICC_IAR0_EL1}}
9 # CHECK: mrs x2, {{icc_hppir1_el1|ICC_HPPIR1_EL1}}
11 # CHECK: mrs x17, {{icc_hppir0_el1|ICC_HPPIR0_EL1}}
13 # CHECK: mrs x29, {{icc_rpr_el1|ICC_RPR_EL1}}
15 # CHECK: mrs x4, {{ich_vtr_el2|ICH_VTR_EL2}}
17 # CHECK: mrs x24, {{ich_eisr_el2|ICH_EISR_EL2}}
19 # CHECK: mrs x9, {{ich_elsr_el2|ICH_ELSR_EL2}}
21 # CHECK: mrs x24, {{icc_bpr1_el1|ICC_BPR1_EL1}}
23 # CHECK: mrs x14, {{icc_bpr0_el1|ICC_BPR0_EL1}}
[all …]
|
| D | basic-a64-instructions.txt | 3316 # CHECK: mrs x9, {{teecr32_el1|TEECR32_EL1}}
3317 # CHECK: mrs x9, {{osdtrrx_el1|OSDTRRX_EL1}}
3318 # CHECK: mrs x9, {{mdccsr_el0|MDCCSR_EL0}}
3319 # CHECK: mrs x9, {{mdccint_el1|MDCCINT_EL1}}
3320 # CHECK: mrs x9, {{mdscr_el1|MDSCR_EL1}}
3321 # CHECK: mrs x9, {{osdtrtx_el1|OSDTRTX_EL1}}
3322 # CHECK: mrs x9, {{dbgdtr_el0|DBGDTR_EL0}}
3323 # CHECK: mrs x9, {{dbgdtrrx_el0|DBGDTRRX_EL0}}
3324 # CHECK: mrs x9, {{oseccr_el1|OSECCR_EL1}}
3325 # CHECK: mrs x9, {{dbgvcr32_el2|DBGVCR32_EL2}}
[all …]
|
| D | arm64-system.txt | 53 # CHECK: mrs x0, S3_0_C11_C0_0
|
| /external/llvm/test/MC/ARM/ |
| D | thumb2-mclass.s | 13 mrs r0, apsr
14 mrs r0, iapsr
15 mrs r0, eapsr
16 mrs r0, xpsr
17 mrs r0, ipsr
18 mrs r0, epsr
19 mrs r0, iepsr
20 mrs r0, msp
21 mrs r0, psp
22 mrs r0, primask
[all …]
|
| D | thumbv7m.s | 13 mrs r0, basepri
14 mrs r0, basepri_max
15 mrs r0, faultmask
17 @ CHECK: mrs r0, basepri @ encoding: [0xef,0xf3,0x11,0x80]
18 @ CHECK: mrs r0, basepri_max @ encoding: [0xef,0xf3,0x12,0x80]
19 @ CHECK: mrs r0, faultmask @ encoding: [0xef,0xf3,0x13,0x80]
34 @ CHECK-V6M-NEXT: mrs r0, basepri
36 @ CHECK-V6M-NEXT: mrs r0, basepri_max
38 @ CHECK-V6M-NEXT: mrs r0, faultmask
|
| D | basic-arm-instructions.s | 1121 mrs r8, apsr
1122 mrs r8, cpsr
1123 mrs r8, spsr
1124 @ CHECK: mrs r8, apsr @ encoding: [0x00,0x80,0x0f,0xe1]
1125 @ CHECK: mrs r8, apsr @ encoding: [0x00,0x80,0x0f,0xe1]
1126 @ CHECK: mrs r8, spsr @ encoding: [0x00,0x80,0x4f,0xe1]
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-tls-execs.ll | 12 ; CHECK: mrs x[[TP:[0-9]+]], TPIDR_EL0
27 ; CHECK: mrs [[TP:x[0-9]+]], TPIDR_EL0
43 ; CHECK: mrs x[[TP:[0-9]+]], TPIDR_EL0
58 ; CHECK: mrs [[TP:x[0-9]+]], TPIDR_EL0
|
| D | arm64-tls-dynamics.ll | 20 ; CHECK: mrs x[[TP:[0-9]+]], TPIDR_EL0
43 ; CHECK: mrs [[TP:x[0-9]+]], TPIDR_EL0
72 ; CHECK: mrs x[[TPIDR:[0-9]+]], TPIDR_EL0
100 ; CHECK: mrs [[TPIDR:x[0-9]+]], TPIDR_EL0
|
| D | nzcv-save.ll | 3 ; CHECK: mrs [[NZCV_SAVE:x[0-9]+]], NZCV
|
| /external/lldb/tools/lldb-perf/lib/ |
| D | MemoryGauge.h | 77 SetMaxResidentSize (mach_vm_size_t mrs) in SetMaxResidentSize() argument
79 m_max_resident_size = mrs; in SetMaxResidentSize()
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb-MSR-MClass.txt | 6 # CHECK: mrs r0, primask
|
| D | thumb-tests.txt | 305 # CHECK: mrs r0, apsr
|
| /external/llvm/test/CodeGen/Thumb/ |
| D | 2012-04-26-M0ISelBug.ll | 2 ; Cortex-M0 doesn't have 32-bit Thumb2 instructions (except for dmb, mrs, etc.)
|
| /external/openssl/crypto/ |
| D | arm64cpuid.S | 17 mrs x0, CNTVCT_EL0
|
| /external/vixl/doc/ |
| D | supported-instructions.md | 574 ### mrs ### subsection
578 void mrs(const Register& rt, SystemRegister sysreg)
|
| /external/valgrind/main/nightly/ |
| D | README.txt | 65 export ABT_DETAILS=`uname -mrs`
|