| /external/valgrind/main/VEX/priv/ |
| D | host_ppc_defs.c | 3143 static UChar* mkFormD ( UChar* p, UInt opc1, in mkFormD() argument
3147 vassert(opc1 < 0x40); in mkFormD()
3151 theInstr = ((opc1<<26) | (r1<<21) | (r2<<16) | (imm)); in mkFormD()
3155 static UChar* mkFormMD ( UChar* p, UInt opc1, UInt r1, UInt r2, in mkFormMD() argument
3159 vassert(opc1 < 0x40); in mkFormMD()
3166 theInstr = ((opc1<<26) | (r1<<21) | (r2<<16) | in mkFormMD()
3172 static UChar* mkFormX ( UChar* p, UInt opc1, UInt r1, UInt r2, in mkFormX() argument
3176 vassert(opc1 < 0x40); in mkFormX()
3182 theInstr = ((opc1<<26) | (r1<<21) | (r2<<16) | in mkFormX()
3187 static UChar* mkFormXO ( UChar* p, UInt opc1, UInt r1, UInt r2, in mkFormXO() argument
[all …]
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| D | guest_ppc_toIR.c | 3211 UChar opc1 = ifieldOPC(theInstr); in dis_int_arith() local
3231 switch (opc1) { in dis_int_arith()
3848 UChar opc1 = ifieldOPC(theInstr); in dis_int_cmp() local
3872 switch (opc1) { in dis_int_cmp()
3968 UChar opc1 = ifieldOPC(theInstr); in dis_int_logic() local
3986 switch (opc1) { in dis_int_logic()
4346 UChar opc1 = ifieldOPC(theInstr); in dis_int_parity() local
4376 if (opc1 != 0x1f || rB_addr || b0) { in dis_int_parity()
4475 UChar opc1 = ifieldOPC(theInstr); in dis_int_rot() local
4499 switch (opc1) { in dis_int_rot()
[all …]
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| D | host_mips_defs.c | 2486 static UChar *mkFormS(UChar * p, UInt opc1, UInt rRD, UInt rRS, UInt rRT, in mkFormS() argument
2490 vassert(opc1 <= 0x3F); in mkFormS()
2497 theInstr = ((opc1 << 26) | (rRS << 21) | (rRT << 16) | (rRD << 11) | in mkFormS()
2503 static UChar *doAMode_IR(UChar * p, UInt opc1, UInt rSD, MIPSAMode * am, in doAMode_IR() argument
2518 if (opc1 < 40) { in doAMode_IR()
2528 p = mkFormI(p, opc1, rA, r_dst, idx); in doAMode_IR()
2530 if (opc1 >= 40) { in doAMode_IR()
2543 static UChar *doAMode_RR(UChar * p, UInt opc1, UInt rSD, MIPSAMode * am, in doAMode_RR() argument
2557 if (opc1 < 40) { in doAMode_RR()
2572 p = mkFormI(p, opc1, rA, r_dst, 0); in doAMode_RR()
[all …]
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| D | host_arm_defs.c | 3853 UInt opc, opc1, opc2; in emit_ARMInstr() local
3906 opc1 = (opc >> 2) & 3; in emit_ARMInstr()
3908 insn = XXXXXXXX(0xE, X1110, BITS4(0,(opc1 >> 1),(opc1 & 1),0), in emit_ARMInstr()
3947 opc1 = (opc >> 2) & 3; in emit_ARMInstr()
3949 insn = XXXXXXXX(0xE, X1110, BITS4(1,(opc1 >> 1),(opc1 & 1),1), in emit_ARMInstr()
3995 opc1 = (opc >> 2) & 3; in emit_ARMInstr()
3997 insn = XXXXXXXX(0xE, X1110, BITS4(0,(opc1 >> 1),(opc1 & 1),1), in emit_ARMInstr()
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| D | guest_mips_toIR.c | 2065 UChar opc1 = get_opcode(theInstr); in dis_instr_branch() local
2093 switch (opc1) { in dis_instr_branch()
2176 UChar opc1 = get_opcode(theInstr); in dis_instr_CVM() local
2191 switch(opc1){ in dis_instr_CVM()
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| /external/chromium_org/sandbox/win/src/ |
| D | policy_low_level_unittest.cc | 394 size_t opc1 = pr_pipe.GetOpcodeCount(); in TEST() local
395 EXPECT_EQ(3, opc1); in TEST()
459 ++opc1; in TEST()
470 EXPECT_EQ((opc1 + opc2 + opc3), tc2); in TEST()
471 EXPECT_EQ((opc1 + opc4), tc3); in TEST()
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| /external/qemu/target-arm/ |
| D | cpu.h | 472 #define ENCODE_CP_REG(cp, is64, crn, crm, opc1, opc2) \ argument
474 ((crm) << 7) | ((opc1) << 3) | (opc2))
616 uint8_t opc1; member
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| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 4672 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4674 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4675 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4678 bits<4> opc1;
4691 let Inst{23-20} = opc1;
4694 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4696 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4697 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4701 bits<4> opc1;
4714 let Inst{23-20} = opc1;
[all …]
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| D | ARMInstrThumb2.td | 4035 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
4043 bits<3> opc1;
4050 let Inst{23-21} = opc1;
4059 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
4060 opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4068 bits<4> opc1;
4074 let Inst{7-4} = opc1;
4081 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4083 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4086 def : t2InstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
[all …]
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreInstrInfo.td | 220 multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> {
221 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
229 multiclass F3R_2RUS_np<bits<5> opc1, bits<5> opc2, string OpcStr> {
230 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
236 multiclass F3R_2RBITP<bits<5> opc1, bits<5> opc2, string OpcStr,
238 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
257 multiclass FL3R_L2RUS<bits<9> opc1, bits<9> opc2, string OpcStr,
259 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
268 multiclass FL3R_L2RBITP<bits<9> opc1, bits<9> opc2, string OpcStr,
270 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrControl.td | 72 multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> {
74 def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm, [],
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| D | X86InstrAVX512.td | 1286 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1288 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
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| /external/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 4971 unsigned opc1 = fieldFromInstruction(Val, 4, 4); in DecodeMRRC2() local
4983 Inst.addOperand(MCOperand::CreateImm(opc1)); in DecodeMRRC2()
|