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Searched refs:outs (Results 1 – 25 of 204) sorted by relevance

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/external/llvm/tools/macho-dump/
Dmacho-dump.cpp58 outs() << " ('segment_name', '"; in DumpSegmentCommandData()
59 outs().write_escaped(Name, /*UseHexEscapes=*/true) << "')\n"; in DumpSegmentCommandData()
60 outs() << " ('vm_addr', " << VMAddr << ")\n"; in DumpSegmentCommandData()
61 outs() << " ('vm_size', " << VMSize << ")\n"; in DumpSegmentCommandData()
62 outs() << " ('file_offset', " << FileOffset << ")\n"; in DumpSegmentCommandData()
63 outs() << " ('file_size', " << FileSize << ")\n"; in DumpSegmentCommandData()
64 outs() << " ('maxprot', " << MaxProt << ")\n"; in DumpSegmentCommandData()
65 outs() << " ('initprot', " << InitProt << ")\n"; in DumpSegmentCommandData()
66 outs() << " ('num_sections', " << NumSections << ")\n"; in DumpSegmentCommandData()
67 outs() << " ('flags', " << Flags << ")\n"; in DumpSegmentCommandData()
[all …]
/external/llvm/lib/Target/X86/
DX86InstrSystem.td18 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)], IIC_RDTSC>,
22 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", [(X86rdtscp)]>, TB;
27 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
28 def UD2B : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB;
31 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", [], IIC_HLT>;
32 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", [], IIC_RSM>, TB;
36 def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>;
37 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3",
50 def INT : Ii8<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap",
54 def SYSCALL : I<0x05, RawFrm, (outs), (ins), "syscall", [], IIC_SYSCALL>, TB;
[all …]
DX86InstrFPStack.td78 def FP32_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP32:$src),
80 def FP32_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP32:$src),
82 def FP32_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP32:$src),
84 def FP64_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP64:$src),
86 def FP64_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP64:$src),
88 def FP64_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP64:$src),
90 def FP80_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP80:$src),
92 def FP80_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP80:$src),
94 def FP80_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP80:$src),
118 def FpPOP_RETVAL : FpI_<(outs RFP80:$dst), (ins), SpecialFP, []>;
[all …]
DX86InstrFormats.td200 class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
212 dag OutOperandList = outs;
298 class I<bits<8> o, Format f, dag outs, dag ins, string asm,
301 : X86Inst<o, f, NoImm, outs, ins, asm, itin, d> {
305 class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm,
308 : X86Inst<o, f, Imm8, outs, ins, asm, itin, d> {
312 class Ii8PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
314 : X86Inst<o, f, Imm8PCRel, outs, ins, asm, itin> {
318 class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm,
320 : X86Inst<o, f, Imm16, outs, ins, asm, itin> {
[all …]
DX86InstrVMX.td19 def INVEPT32 : I<0x80, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
22 def INVEPT64 : I<0x80, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
26 def INVVPID32 : I<0x81, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
29 def INVVPID64 : I<0x81, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
33 def VMCALL : I<0x01, MRM_C1, (outs), (ins), "vmcall", []>, TB;
34 def VMCLEARm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
37 def VMFUNC : I<0x01, MRM_D4, (outs), (ins), "vmfunc", []>, TB;
39 def VMLAUNCH : I<0x01, MRM_C2, (outs), (ins), "vmlaunch", []>, TB;
41 def VMRESUME : I<0x01, MRM_C3, (outs), (ins), "vmresume", []>, TB;
42 def VMPTRLDm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
[all …]
DX86InstrControl.td24 def RETL : I <0xC3, RawFrm, (outs), (ins variable_ops),
27 def RETQ : I <0xC3, RawFrm, (outs), (ins variable_ops),
30 def RETW : I <0xC3, RawFrm, (outs), (ins),
33 def RETIL : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
37 def RETIQ : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
41 def RETIW : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt),
44 def LRETL : I <0xCB, RawFrm, (outs), (ins),
46 def LRETQ : RI <0xCB, RawFrm, (outs), (ins),
48 def LRETW : I <0xCB, RawFrm, (outs), (ins),
50 def LRETIL : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
[all …]
DX86InstrShiftRotate.td20 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
23 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
26 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
29 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
34 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
39 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
43 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
47 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst),
56 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
58 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
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/external/llvm/lib/Target/XCore/
DXCoreInstrFormats.td13 class InstXCore<int sz, dag outs, dag ins, string asmstr, list<dag> pattern>
18 dag OutOperandList = outs;
27 class PseudoInstXCore<dag outs, dag ins, string asmstr, list<dag> pattern>
28 : InstXCore<0, outs, ins, asmstr, pattern> {
36 class _F3R<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
37 : InstXCore<2, outs, ins, asmstr, pattern> {
45 class _F3RImm<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
46 : _F3R<opc, outs, ins, asmstr, pattern> {
50 class _FL3R<bits<9> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
51 : InstXCore<4, outs, ins, asmstr, pattern> {
[all …]
DXCoreInstrInfo.td221 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
224 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
230 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
232 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
238 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
241 def _2rus : _F2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
247 _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
252 _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
259 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
262 def _l2rus : _FL2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
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/external/llvm/tools/llvm-objdump/
DCOFFDump.cpp97 outs() << format(" 0x%02x: ", unsigned(UCs[0].u.CodeOffset)) in printUnwindCode()
101 outs() << " " << getUnwindRegisterName(UCs[0].getOpInfo()); in printUnwindCode()
105 outs() << " " << UCs[1].FrameOffset; in printUnwindCode()
107 outs() << " " << UCs[1].FrameOffset in printUnwindCode()
112 outs() << " " << ((UCs[0].getOpInfo() + 1) * 8); in printUnwindCode()
115 outs() << " "; in printUnwindCode()
118 outs() << " " << getUnwindRegisterName(UCs[0].getOpInfo()) in printUnwindCode()
122 outs() << " " << getUnwindRegisterName(UCs[0].getOpInfo()) in printUnwindCode()
127 outs() << " XMM" << static_cast<uint32_t>(UCs[0].getOpInfo()) in printUnwindCode()
131 outs() << " XMM" << UCs[0].getOpInfo() in printUnwindCode()
[all …]
DELFDump.cpp26 outs() << "Program Header:\n"; in printProgramHeaders()
32 outs() << " LOAD "; in printProgramHeaders()
35 outs() << " STACK "; in printProgramHeaders()
38 outs() << "EH_FRAME "; in printProgramHeaders()
41 outs() << " INTERP "; in printProgramHeaders()
44 outs() << " DYNAMIC "; in printProgramHeaders()
47 outs() << " PHDR "; in printProgramHeaders()
50 outs() << " TLS "; in printProgramHeaders()
53 outs() << " UNKNOWN "; in printProgramHeaders()
58 outs() << "off " in printProgramHeaders()
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/external/llvm/tools/bugpoint/
DFindBugs.cpp36 outs() << "Starting bug finding procedure...\n\n"; in runManyPasses()
41 outs() << "\n"; in runManyPasses()
43 outs() << "Generating reference output from raw program: \n"; in runManyPasses()
60 outs() << "Running selected passes on program to test for crash: "; in runManyPasses()
62 outs() << "-" << PassesToRun[i] << " "; in runManyPasses()
67 outs() << "\n"; in runManyPasses()
68 outs() << "Optimizer passes caused failure!\n\n"; in runManyPasses()
72 outs() << "Combination " << num << " optimized successfully!\n"; in runManyPasses()
78 outs() << "Running the code generator to test for a crash: "; in runManyPasses()
82 outs() << "\n*** compileProgram threw an exception: "; in runManyPasses()
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DBugDriver.cpp126 outs() << "Read input file : '" << Filenames[0] << "'\n"; in addSources()
132 outs() << "Linking in input file: '" << Filenames[i] << "'\n"; in addSources()
142 outs() << "*** All input ok\n"; in addSources()
168 outs() << "Running selected passes on program to test for crash: "; in run()
177 outs() << "Running the code generator to test for a crash: "; in run()
181 outs() << Error; in run()
184 outs() << '\n'; in run()
192 outs() << "Generating reference output from raw program: "; in run()
207 outs() << "*** Checking the code generator...\n"; in run()
214 outs() << "\n*** Output matches: Debugging miscompilation!\n"; in run()
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/external/llvm/lib/Target/MSP430/
DMSP430InstrFormats.td54 class MSP430Inst<dag outs, dag ins, SizeVal sz, Format f,
60 dag OutOperandList = outs;
78 dag outs, dag ins, string asmstr, list<dag> pattern>
79 : MSP430Inst<outs, ins, sz, DoubleOpFrm, asmstr> {
93 dag outs, dag ins, string asmstr, list<dag> pattern>
94 : IForm<opcode, dest, 1, src, sz, outs, ins, asmstr, pattern>;
97 dag outs, dag ins, string asmstr, list<dag> pattern>
98 : IForm8<opcode, DstReg, SrcReg, Size2Bytes, outs, ins, asmstr, pattern>;
101 dag outs, dag ins, string asmstr, list<dag> pattern>
102 : IForm8<opcode, DstReg, SrcImm, Size4Bytes, outs, ins, asmstr, pattern>;
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DMSP430InstrInfo.td116 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i16imm:$amt),
119 def ADJCALLSTACKUP : Pseudo<(outs), (ins i16imm:$amt1, i16imm:$amt2),
125 def Select8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$src2, i8imm:$cc),
129 def Select16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR16:$src2, i8imm:$cc),
134 def Shl8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt),
137 def Shl16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR8:$cnt),
140 def Sra8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt),
143 def Sra16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR8:$cnt),
146 def Srl8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt),
149 def Srl16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR8:$cnt),
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/external/llvm/tools/llvm-bcanalyzer/
Dllvm-bcanalyzer.cpp336 if (Dump) outs() << Indent << "<BLOCKINFO_BLOCK/>\n"; in ParseBlock()
350 outs() << Indent << "<"; in ParseBlock()
352 outs() << BlockName; in ParseBlock()
354 outs() << "UnknownBlock" << BlockID; in ParseBlock()
357 outs() << " BlockID=" << BlockID; in ParseBlock()
359 outs() << " NumWords=" << NumWords in ParseBlock()
382 outs() << Indent << "</"; in ParseBlock()
384 outs() << BlockName << ">\n"; in ParseBlock()
386 outs() << "UnknownBlock" << BlockID << ">\n"; in ParseBlock()
432 outs() << Indent << " <"; in ParseBlock()
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/external/llvm/lib/Target/Sparc/
DSparcInstrFormats.td10 class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern>
20 dag OutOperandList = outs;
34 class F2<dag outs, dag ins, string asmstr, list<dag> pattern>
35 : InstSP<outs, ins, asmstr, pattern> {
45 class F2_1<bits<3> op2Val, dag outs, dag ins, string asmstr, list<dag> pattern>
46 : F2<outs, ins, asmstr, pattern> {
54 class F2_2<bits<3> op2Val, bit annul, dag outs, dag ins, string asmstr,
55 list<dag> pattern> : F2<outs, ins, asmstr, pattern> {
64 dag outs, dag ins, string asmstr, list<dag> pattern>
65 : InstSP<outs, ins, asmstr, pattern> {
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/external/llvm/tools/llvm-size/
Dllvm-size.cpp86 outs() << ToolName << ": error reading file: " << ec.message() << ".\n"; in error()
87 outs().flush(); in error()
133 outs() << "Segment " << Seg.segname << ": " in PrintDarwinSectionSizes()
136 outs() << " (vmaddr 0x" << format("%" PRIx64, Seg.vmaddr) << " fileoff " in PrintDarwinSectionSizes()
138 outs() << "\n"; in PrintDarwinSectionSizes()
144 outs() << "\tSection (" << format("%.16s", &Sec.segname) << ", " in PrintDarwinSectionSizes()
147 outs() << "\tSection " << format("%.16s", &Sec.sectname) << ": "; in PrintDarwinSectionSizes()
148 outs() << format(fmt.str().c_str(), Sec.size); in PrintDarwinSectionSizes()
150 outs() << " (addr 0x" << format("%" PRIx64, Sec.addr) << " offset " in PrintDarwinSectionSizes()
152 outs() << "\n"; in PrintDarwinSectionSizes()
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/external/llvm/lib/Target/PowerPC/
DPPCInstrVSX.td51 (outs vsfrc:$XT), (ins memrr:$src),
56 (outs vsrc:$XT), (ins memrr:$src),
61 (outs vsrc:$XT), (ins memrr:$src),
65 (outs vsrc:$XT), (ins memrr:$src),
72 (outs), (ins vsfrc:$XT, memrr:$dst),
77 (outs), (ins vsrc:$XT, memrr:$dst),
82 (outs), (ins vsrc:$XT, memrr:$dst),
89 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
93 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
98 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
[all …]
DPPCInstr64Bit.td85 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
88 def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
93 def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi),
96 def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi),
103 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>,
108 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
110 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
115 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
117 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
127 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func),
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/external/llvm/lib/Target/Hexagon/
DHexagonInstrFormatsV4.td31 class NVInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
33 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeNV>;
35 class NVInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
37 : NVInst<outs, ins, asmstr, pattern, cstr, itin>;
40 class NVInstPost_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
42 : NVInst<outs, ins, asmstr, pattern, cstr, itin>;
46 class NVInstPI_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
48 : NVInst<outs, ins, asmstr, pattern, cstr, itin>;
51 class NCJInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
53 : NVInst<outs, ins, asmstr, pattern, cstr>;
[all …]
DHexagonInstrFormats.td85 class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
90 dag OutOperandList = outs;
199 class LDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
201 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>;
204 class LDInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [],
206 : LDInst<outs, ins, asmstr, pattern, cstr>;
208 class CONSTLDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
210 : LDInst<outs, ins, asmstr, pattern, cstr>;
214 class LDInstPost<dag outs, dag ins, string asmstr, list<dag> pattern = [],
216 : LDInst<outs, ins, asmstr, pattern, cstr>;
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/external/llvm/lib/Target/Mips/
DMips16InstrFormats.td36 class MipsInst16_Base<dag outs, dag ins, string asmstr, list<dag> pattern,
42 let OutOperandList = outs;
55 class MipsInst16<dag outs, dag ins, string asmstr, list<dag> pattern,
57 MipsInst16_Base<outs, ins, asmstr, pattern, itin>
72 class MipsInst16_32<dag outs, dag ins, string asmstr, list<dag> pattern,
74 MipsInst16_Base<outs, ins, asmstr, pattern, itin>
82 class MipsInst16_EXTEND<dag outs, dag ins, string asmstr, list<dag> pattern,
84 MipsInst16_32<outs, ins, asmstr, pattern, itin>
92 class MipsPseudo16<dag outs, dag ins, string asmstr, list<dag> pattern>:
93 MipsInst16<outs, ins, asmstr, pattern, IIPseudo> {
[all …]
/external/llvm/tools/llvm-nm/
Dllvm-nm.cpp294 outs() << SymbolAddrStr << ' '; in darwinPrintSymbol()
300 outs() << "(common) "; in darwinPrintSymbol()
302 outs() << "(alignment 2^" << (int)MachO::GET_COMM_ALIGN(NDesc) << ") "; in darwinPrintSymbol()
305 outs() << "(prebound "; in darwinPrintSymbol()
307 outs() << "("; in darwinPrintSymbol()
310 outs() << "undefined [lazy bound]) "; in darwinPrintSymbol()
313 outs() << "undefined [private lazy bound]) "; in darwinPrintSymbol()
316 outs() << "undefined [private]) "; in darwinPrintSymbol()
318 outs() << "undefined) "; in darwinPrintSymbol()
322 outs() << "(absolute) "; in darwinPrintSymbol()
[all …]
/external/llvm/lib/Target/R600/
DSIInstrFormats.td14 class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
15 AMDGPUInst<outs, ins, asm, pattern>, PredicateControl {
40 class Enc32 <dag outs, dag ins, string asm, list<dag> pattern> :
41 InstSI <outs, ins, asm, pattern> {
47 class Enc64 <dag outs, dag ins, string asm, list<dag> pattern> :
48 InstSI <outs, ins, asm, pattern> {
54 class VOP3Common <dag outs, dag ins, string asm, list<dag> pattern> :
55 Enc64 <outs, ins, asm, pattern> {
68 class SOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
69 Enc32<outs, ins, asm, pattern> {
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