| /external/mesa3d/src/mesa/drivers/dri/r200/ |
| D | r200_blit.c | 74 static inline void emit_vtx_state(struct r200_context *r200) in emit_vtx_state() argument
76 BATCH_LOCALS(&r200->radeon); in emit_vtx_state()
79 if (r200->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) { in emit_vtx_state()
99 static void inline emit_tx_setup(struct r200_context *r200, in emit_tx_setup() argument
109 BATCH_LOCALS(&r200->radeon); in emit_tx_setup()
297 static inline void emit_cb_setup(struct r200_context *r200, in emit_cb_setup() argument
307 BATCH_LOCALS(&r200->radeon); in emit_cb_setup()
358 static GLboolean validate_buffers(struct r200_context *r200, in validate_buffers() argument
364 radeon_cs_space_reset_bos(r200->radeon.cmdbuf.cs); in validate_buffers()
366 ret = radeon_cs_space_check_with_bo(r200->radeon.cmdbuf.cs, in validate_buffers()
[all …]
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| D | r200_state_init.c | 326 r200ContextPtr r200 = R200_CONTEXT(ctx); in check_rrb() local
328 rrb = radeon_get_colorbuffer(&r200->radeon); in check_rrb()
337 r200ContextPtr r200 = R200_CONTEXT(ctx); in check_polygon_stipple() local
338 if (r200->hw.set.cmd[SET_RE_CNTL] & R200_STIPPLE_ENABLE) in check_polygon_stipple()
345 r200ContextPtr r200 = R200_CONTEXT(ctx); in mtl_emit() local
346 BATCH_LOCALS(&r200->radeon); in mtl_emit()
357 r200ContextPtr r200 = R200_CONTEXT(ctx); in lit_emit() local
358 BATCH_LOCALS(&r200->radeon); in lit_emit()
369 r200ContextPtr r200 = R200_CONTEXT(ctx); in ptp_emit() local
370 BATCH_LOCALS(&r200->radeon); in ptp_emit()
[all …]
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| D | r200_blit.h | 31 void r200_blit_init(struct r200_context *r200);
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| D | Makefile.am | 36 -I$(top_srcdir)/src/mesa/drivers/dri/r200/server \
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| D | Doxyfile | 6 PROJECT_NAME = r200
60 INPUT = /home/temp/Mesa/src/drv/r200
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| D | r200_state.c | 1577 r200ContextPtr r200 = R200_CONTEXT(ctx); in r200_vtbl_update_scissor() local
1581 R200_SET_STATE(r200, set, SET_RE_CNTL, R200_SCISSOR_ENABLE | r200->hw.set.cmd[SET_RE_CNTL]); in r200_vtbl_update_scissor()
1583 if (r200->radeon.state.scissor.enabled) { in r200_vtbl_update_scissor()
1584 x1 = r200->radeon.state.scissor.rect.x1; in r200_vtbl_update_scissor()
1585 y1 = r200->radeon.state.scissor.rect.y1; in r200_vtbl_update_scissor()
1586 x2 = r200->radeon.state.scissor.rect.x2; in r200_vtbl_update_scissor()
1587 y2 = r200->radeon.state.scissor.rect.y2; in r200_vtbl_update_scissor()
1589 rrb = radeon_get_colorbuffer(&r200->radeon); in r200_vtbl_update_scissor()
1596 R200_SET_STATE(r200, sci, SCI_XY_1, x1 | (y1 << 16)); in r200_vtbl_update_scissor()
1597 R200_SET_STATE(r200, sci, SCI_XY_2, x2 | (y2 << 16)); in r200_vtbl_update_scissor()
[all …]
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| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/r200/ |
| D | r200_blit.c | 74 static inline void emit_vtx_state(struct r200_context *r200) in emit_vtx_state() argument
76 BATCH_LOCALS(&r200->radeon); in emit_vtx_state()
79 if (r200->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) { in emit_vtx_state()
99 static void inline emit_tx_setup(struct r200_context *r200, in emit_tx_setup() argument
109 BATCH_LOCALS(&r200->radeon); in emit_tx_setup()
297 static inline void emit_cb_setup(struct r200_context *r200, in emit_cb_setup() argument
307 BATCH_LOCALS(&r200->radeon); in emit_cb_setup()
358 static GLboolean validate_buffers(struct r200_context *r200, in validate_buffers() argument
364 radeon_cs_space_reset_bos(r200->radeon.cmdbuf.cs); in validate_buffers()
366 ret = radeon_cs_space_check_with_bo(r200->radeon.cmdbuf.cs, in validate_buffers()
[all …]
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| D | r200_state_init.c | 326 r200ContextPtr r200 = R200_CONTEXT(ctx); in check_rrb() local
328 rrb = radeon_get_colorbuffer(&r200->radeon); in check_rrb()
337 r200ContextPtr r200 = R200_CONTEXT(ctx); in check_polygon_stipple() local
338 if (r200->hw.set.cmd[SET_RE_CNTL] & R200_STIPPLE_ENABLE) in check_polygon_stipple()
345 r200ContextPtr r200 = R200_CONTEXT(ctx); in mtl_emit() local
346 BATCH_LOCALS(&r200->radeon); in mtl_emit()
357 r200ContextPtr r200 = R200_CONTEXT(ctx); in lit_emit() local
358 BATCH_LOCALS(&r200->radeon); in lit_emit()
369 r200ContextPtr r200 = R200_CONTEXT(ctx); in ptp_emit() local
370 BATCH_LOCALS(&r200->radeon); in ptp_emit()
[all …]
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| D | r200_blit.h | 31 void r200_blit_init(struct r200_context *r200);
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| D | Makefile.am | 36 -I$(top_srcdir)/src/mesa/drivers/dri/r200/server \
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| D | Doxyfile | 6 PROJECT_NAME = r200
60 INPUT = /home/temp/Mesa/src/drv/r200
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| D | r200_state.c | 1577 r200ContextPtr r200 = R200_CONTEXT(ctx); in r200_vtbl_update_scissor() local
1581 R200_SET_STATE(r200, set, SET_RE_CNTL, R200_SCISSOR_ENABLE | r200->hw.set.cmd[SET_RE_CNTL]); in r200_vtbl_update_scissor()
1583 if (r200->radeon.state.scissor.enabled) { in r200_vtbl_update_scissor()
1584 x1 = r200->radeon.state.scissor.rect.x1; in r200_vtbl_update_scissor()
1585 y1 = r200->radeon.state.scissor.rect.y1; in r200_vtbl_update_scissor()
1586 x2 = r200->radeon.state.scissor.rect.x2; in r200_vtbl_update_scissor()
1587 y2 = r200->radeon.state.scissor.rect.y2; in r200_vtbl_update_scissor()
1589 rrb = radeon_get_colorbuffer(&r200->radeon); in r200_vtbl_update_scissor()
1596 R200_SET_STATE(r200, sci, SCI_XY_1, x1 | (y1 << 16)); in r200_vtbl_update_scissor()
1597 R200_SET_STATE(r200, sci, SCI_XY_2, x2 | (y2 << 16)); in r200_vtbl_update_scissor()
[all …]
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| /external/mesa3d/src/mesa/drivers/dri/ |
| D | Makefile.am | 20 SUBDIRS+=r200 subdir
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| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/ |
| D | Makefile.am | 20 SUBDIRS+=r200 subdir
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| /external/mesa3d/src/mesa/drivers/dri/common/xmlpool/ |
| D | nl.po | 194 "Enable hack to allow larger textures with texture compression on radeon/r200"
197 "een radeon/r200"
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| D | fr.po | 189 "Enable hack to allow larger textures with texture compression on radeon/r200"
192 "compression de textures sur radeon/r200"
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| D | es.po | 185 msgid "Enable hack to allow larger textures with texture compression on radeon/r200"
186 …r \"hack\" para permitir texturas más grandes con compresión de textura activada en la Radeon/r200"
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| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/common/xmlpool/ |
| D | nl.po | 194 "Enable hack to allow larger textures with texture compression on radeon/r200"
197 "een radeon/r200"
|
| D | fr.po | 189 "Enable hack to allow larger textures with texture compression on radeon/r200"
192 "compression de textures sur radeon/r200"
|
| D | es.po | 185 msgid "Enable hack to allow larger textures with texture compression on radeon/r200"
186 …r \"hack\" para permitir texturas más grandes con compresión de textura activada en la Radeon/r200"
|
| /external/chromium_org/third_party/mesa/src/ |
| D | configure.ac | 1037 DRI_DIRS="i915 i965 nouveau r200 radeon swrast"
1043 DRI_DIRS="r200 radeon swrast"
1049 DRI_DIRS="r200 radeon swrast"
1059 DRI_DIRS="i915 i965 nouveau r200 radeon swrast"
1079 DRI_DIRS="i915 i965 nouveau r200 radeon swrast"
1149 *radeon*|*r200*)
1157 r200)
2024 src/mesa/drivers/dri/r200/Makefile
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| /external/mesa3d/ |
| D | configure.ac | 1037 DRI_DIRS="i915 i965 nouveau r200 radeon swrast"
1043 DRI_DIRS="r200 radeon swrast"
1049 DRI_DIRS="r200 radeon swrast"
1059 DRI_DIRS="i915 i965 nouveau r200 radeon swrast"
1079 DRI_DIRS="i915 i965 nouveau r200 radeon swrast"
1149 *radeon*|*r200*)
1157 r200)
2024 src/mesa/drivers/dri/r200/Makefile
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| /external/llvm/test/Analysis/CostModel/ARM/ |
| D | cast.ll | 440 %r200 = uitofp <4 x i1> undef to <4 x double>
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| /external/mesa3d/docs/ |
| D | VERSIONS | 1448 - r200: enable GL_ARB_texture_env_crossbar, separate the texture
1450 - r200: add support for GL_ATI_fragment_shader
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| /external/chromium_org/third_party/mesa/src/docs/ |
| D | VERSIONS | 1448 - r200: enable GL_ARB_texture_env_crossbar, separate the texture
1450 - r200: add support for GL_ATI_fragment_shader
|