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Searched refs:rM (Results 1 – 25 of 30) sorted by relevance

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/external/valgrind/main/VEX/priv/
Dguest_arm_toIR.c1734 UInt rM /* only for debug printing */ in compute_result_and_C_after_LSL_by_imm5() argument
1742 DIS(buf, "r%u", rM); in compute_result_and_C_after_LSL_by_imm5()
1754 DIS(buf, "r%u, LSL #%u", rM, shift_amt); in compute_result_and_C_after_LSL_by_imm5()
1764 UInt rM, UInt rS /* only for debug printing */ in compute_result_and_C_after_LSL_by_reg() argument
1828 DIS(buf, "r%u, LSL r%u", rM, rS); in compute_result_and_C_after_LSL_by_reg()
1837 UInt rM /* only for debug printing */ in compute_result_and_C_after_LSR_by_imm5() argument
1851 DIS(buf, "r%u, LSR #0(a.k.a. 32)", rM); in compute_result_and_C_after_LSR_by_imm5()
1866 DIS(buf, "r%u, LSR #%u", rM, shift_amt); in compute_result_and_C_after_LSR_by_imm5()
1876 UInt rM, UInt rS /* only for debug printing */ in compute_result_and_C_after_LSR_by_reg() argument
1938 DIS(buf, "r%u, LSR r%u", rM, rS); in compute_result_and_C_after_LSR_by_reg()
[all …]
Dhost_arm_isel.c2316 HReg rM = newVRegD(env); in iselNeon64Expr_wrk() local
2330 addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rM, argL, 4, False)); in iselNeon64Expr_wrk()
2332 addInstr(env, ARMInstr_NDual(ARMneon_TRN, rD, rM, size, False)); in iselNeon64Expr_wrk()
2333 return resRd ? rD : rM; in iselNeon64Expr_wrk()
2342 HReg rM = newVRegD(env); in iselNeon64Expr_wrk() local
2354 addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rM, argL, 4, False)); in iselNeon64Expr_wrk()
2356 addInstr(env, ARMInstr_NDual(ARMneon_ZIP, rD, rM, size, False)); in iselNeon64Expr_wrk()
2357 return resRd ? rD : rM; in iselNeon64Expr_wrk()
2366 HReg rM = newVRegD(env); in iselNeon64Expr_wrk() local
2378 addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rM, argL, 4, False)); in iselNeon64Expr_wrk()
[all …]
Dhost_arm64_defs.c4045 UInt rM = iregNo(i->ARM64in.Arith.argR->ARM64riA.R.reg); in emit_ARM64Instr() local
4048 X01011000, rM, X000000, rN, rD in emit_ARM64Instr()
4074 UInt rM = iregNo(i->ARM64in.Cmp.argR->ARM64riA.R.reg); in emit_ARM64Instr() local
4076 X01011000, rM, X000000, rN, rD); in emit_ARM64Instr()
4114 UInt rM = iregNo(argR->ARM64riL.R.reg); in emit_ARM64Instr() local
4115 vassert(rM < 31); in emit_ARM64Instr()
4116 *p++ = X_3_8_5_6_5_5(opc, X01010000, rM, X000000, rN, rD); in emit_ARM64Instr()
4176 UInt rM = iregNo(argR->ARM64ri6.R.reg); in emit_ARM64Instr() local
4177 vassert(rM < 31); in emit_ARM64Instr()
4185 *p++ = X_3_8_5_6_5_5(X100, X11010110, rM, subOpc, rN, rD); in emit_ARM64Instr()
Dhost_arm_defs.c379 ARMAModeN *mkARMAModeN_RR ( HReg rN, HReg rM ) { in mkARMAModeN_RR() argument
383 am->ARMamN.RR.rM = rM; in mkARMAModeN_RR()
399 addHRegUse(u, HRmRead, am->ARMamN.RR.rM); in addRegUsage_ARMAModeN()
408 am->ARMamN.RR.rM = lookupHRegRemap(m, am->ARMamN.RR.rM); in mapRegs_ARMAModeN()
422 ppHRegARM(am->ARMamN.RR.rM); in ppARMAModeN()
3017 UInt rM = iregNo(i->ARMin.Shift.argL); in emit_ARMInstr() local
3026 instr |= XXXXX__X(X1110,X0001,X1010,X0000,rD, /* _ _ */ rM); in emit_ARMInstr()
3817 regM = iregNo(i->ARMin.NLdStQ.amode->ARMamN.RR.rM); in emit_ARMInstr()
3837 regM = iregNo(i->ARMin.NLdStD.amode->ARMamN.RR.rM); in emit_ARMInstr()
Dhost_arm_defs.h213 HReg rM; member
Dguest_arm64_toIR.c2310 UInt rM = INSN(20,16); in dis_ARM64_data_processing_register() local
2322 IRTemp argR = getShiftedIRegOrZR(is64, sh, imm6, rM, False); in dis_ARM64_data_processing_register()
2333 nameIRegOrZR(is64, rM), nameSH(sh), imm6); in dis_ARM64_data_processing_register()
2353 UInt rM = INSN(20,16); in dis_ARM64_data_processing_register() local
2369 assign(argR, getIRegOrZR(is64, rM)); in dis_ARM64_data_processing_register()
2396 nameIRegOrZR(is64, rM)); in dis_ARM64_data_processing_register()
2420 UInt rM = INSN(20,16); in dis_ARM64_data_processing_register() local
2431 IRTemp argR = getShiftedIRegOrZR(is64, sh, imm6, rM, bN == 1); in dis_ARM64_data_processing_register()
2453 nameIRegOrZR(is64, rM)); in dis_ARM64_data_processing_register()
2457 nameIRegOrZR(is64, rM), nameSH(sh), imm6); in dis_ARM64_data_processing_register()
/external/llvm/test/CodeGen/SystemZ/
Dasm-16.ll11 %val = call i32 asm "blah $0 $1", "=&r,rM" (i32 2147483646)
20 %val = call i32 asm "blah $0 $1", "=&r,rM" (i32 2147483647)
30 %val = call i32 asm "blah $0 $1", "=&r,rM" (i32 2147483648)
Dasm-15.ll11 %val = call i32 asm "blah $0 $1", "=&r,rM" (i32 2147483646)
20 %val = call i32 asm "blah $0 $1", "=&r,rM" (i32 2147483647)
30 %val = call i32 asm "blah $0 $1", "=&r,rM" (i32 2147483648)
/external/compiler-rt/lib/builtins/arm/
Dsync-ops.h47 #define MINMAX_4(rD, rN, rM, cmp_kind) \ argument
48 cmp rN, rM ; \
49 mov rD, rM ; \
Dsync_fetch_and_nand_4.S17 #define nand_4(rD, rN, rM) bic rD, rN, rM argument
Dsync_fetch_and_and_4.S17 #define and_4(rD, rN, rM) and rD, rN, rM argument
Dsync_fetch_and_sub_4.S18 #define sub_4(rD, rN, rM) sub rD, rN, rM argument
Dsync_fetch_and_or_4.S17 #define or_4(rD, rN, rM) orr rD, rN, rM argument
Dsync_fetch_and_xor_4.S17 #define xor_4(rD, rN, rM) eor rD, rN, rM argument
Dsync_fetch_and_add_4.S18 #define add_4(rD, rN, rM) add rD, rN, rM argument
Dsync_fetch_and_umin_4.S17 #define umin_4(rD, rN, rM) MINMAX_4(rD, rN, rM, lo) argument
Dsync_fetch_and_max_4.S17 #define max_4(rD, rN, rM) MINMAX_4(rD, rN, rM, gt) argument
Dsync_fetch_and_umax_4.S17 #define umax_4(rD, rN, rM) MINMAX_4(rD, rN, rM, hi) argument
Dsync_fetch_and_min_4.S17 #define min_4(rD, rN, rM) MINMAX_4(rD, rN, rM, lt) argument
/external/svox/pico_resources/tools/LingwareBuilding/PicoLingware_source_files/pkb/de-DE/
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/external/svox/pico_resources/tools/LingwareBuilding/PicoLingware_source_files/pkb/en-GB/
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/external/sonivox/jet_tools/JetCreator/
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/external/svox/pico_resources/tools/LingwareBuilding/PicoLingware_source_files/pkb/it-IT/
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