/external/llvm/test/CodeGen/Mips/ |
D | bswap.ll | 9 ; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16 13 ; MIPS64: rotr ${{[0-9]+}}, $[[R0]], 16 36 ; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16 38 ; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16 76 ; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16 78 ; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16 80 ; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16 82 ; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16 86 ; MIPS64: rotr ${{[0-9]+}}, $[[R0]], 16 88 ; MIPS64: rotr ${{[0-9]+}}, $[[R0]], 16 [all …]
|
D | rotate.ll | 15 ; CHECK: rotr $2, $4, 22 36 ; CHECK: rotr $2, $4, 10
|
/external/wpa_supplicant_8/src/crypto/ |
D | aes_i.h | 70 static inline u32 rotr(u32 val, int bits) in rotr() function 76 #define TE1(i) rotr(Te0[((i) >> 16) & 0xff], 8) 77 #define TE2(i) rotr(Te0[((i) >> 8) & 0xff], 16) 78 #define TE3(i) rotr(Te0[(i) & 0xff], 24) 94 #define TD1(i) rotr(Td0[((i) >> 16) & 0xff], 8) 95 #define TD2(i) rotr(Td0[((i) >> 8) & 0xff], 16) 96 #define TD3(i) rotr(Td0[(i) & 0xff], 24) 102 #define TD1_(i) rotr(Td0[(i) & 0xff], 8) 103 #define TD2_(i) rotr(Td0[(i) & 0xff], 16) 104 #define TD3_(i) rotr(Td0[(i) & 0xff], 24)
|
/external/openssl/crypto/des/asm/ |
D | crypt586.pl | 109 &rotr( $t, 4 ); 174 { &rotr($tt, 3-$lr); } 180 { &rotr($r, 2-$lr); } 193 else { &rotr($r, $lr-2); } 199 else { &rotr($l, $lr-3); } 207 &rotr($tt , 4);
|
D | des-586.pl | 187 &rotr($L,3); # r 189 &rotr($R,3); # l 217 &rotr( $t, 4 ); 279 { &rotr($tt, 3-$lr); } 285 { &rotr($r, 2-$lr); } 298 else { &rotr($r, $lr-2); } 304 else { &rotr($l, $lr-3); } 312 &rotr($tt , 4);
|
/external/llvm/test/TableGen/ |
D | SetTheory.td | 115 // The 'rotr' operator rotates right, but also accepts a negative shift. 116 def rotr; 117 def S7a : Set<(rotr S0f, 0)>; 118 def S7b : Set<(rotr S0f, 1)>; 119 def S7c : Set<(rotr S0f, 3)>; 120 def S7d : Set<(rotr S0f, 4)>; 121 def S7e : Set<(rotr S0f, 5)>; 122 def S7f : Set<(rotr S0f, -1)>; 123 def S7g : Set<(rotr S0f, -4)>; 124 def S7h : Set<(rotr S0f, -5)>;
|
/external/llvm/test/MC/Mips/ |
D | micromips-shift-instructions.s | 16 # CHECK-EL: rotr $9, $6, 7 # encoding: [0x26,0x01,0xc0,0x38] 27 # CHECK-EB: rotr $9, $6, 7 # encoding: [0x01,0x26,0x38,0xc0] 35 rotr $9, $6, 7
|
D | mips-alu-instructions.s | 19 # CHECK: rotr $9, $6, 7 # encoding: [0xc2,0x49,0x26,0x00] 50 rotr $9, $6, 7
|
D | mips64-alu-instructions.s | 17 # CHECK: rotr $9, $6, 7 # encoding: [0xc2,0x49,0x26,0x00] 45 rotr $9, $6, 7
|
/external/llvm/unittests/ADT/ |
D | APIntTest.cpp | 158 EXPECT_EQ(one, one.rotr(0)); in TEST() 159 EXPECT_EQ(one, one.rotr(1)); in TEST() 508 EXPECT_EQ(APInt(8, 16), APInt(8, 16).rotr(0)); in TEST() 509 EXPECT_EQ(APInt(8, 8), APInt(8, 16).rotr(1)); in TEST() 510 EXPECT_EQ(APInt(8, 4), APInt(8, 16).rotr(2)); in TEST() 511 EXPECT_EQ(APInt(8, 1), APInt(8, 16).rotr(4)); in TEST() 512 EXPECT_EQ(APInt(8, 16), APInt(8, 16).rotr(8)); in TEST() 514 EXPECT_EQ(APInt(8, 1), APInt(8, 1).rotr(0)); in TEST() 515 EXPECT_EQ(APInt(8, 128), APInt(8, 1).rotr(1)); in TEST() 516 EXPECT_EQ(APInt(8, 64), APInt(8, 1).rotr(2)); in TEST() [all …]
|
/external/llvm/test/CodeGen/AArch64/ |
D | arm64-regress-interphase-shift.ll | 5 ; unselectable "rotr" node: (i32 (rotr i32, i64)).
|
/external/chromium_org/third_party/skia/bench/ |
D | FontCacheBench.cpp | 57 static uint32_t rotr(uint32_t value, unsigned bits) { in rotr() function 104 if (false) rotr(0, 0); in FontCacheEfficiency()
|
/external/skia/bench/ |
D | FontCacheBench.cpp | 56 static uint32_t rotr(uint32_t value, unsigned bits) { in rotr() function 114 if (false) rotr(0, 0); in FontCacheEfficiency()
|
/external/openssl/crypto/bf/asm/ |
D | bf-686.pl | 95 &rotr( $R, 16); 101 &rotr( $R, 16);
|
/external/llvm/test/MC/Mips/mips32r2/ |
D | valid.s | 136 … rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2] 137 … rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2]
|
/external/valgrind/main/none/tests/mips64/ |
D | shift_instructions.stdout.exp-mips64r2 | 18433 rotr $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000 18434 rotr $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f 18435 rotr $a0, $a1, 0x0f :: rt 0x0, rs 0x0, imm 0x000f 18436 rotr $s0, $s1, 0x03 :: rt 0x0, rs 0x0, imm 0x0003 18437 rotr $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000 18438 rotr $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f 18439 rotr $a0, $a1, 0x0f :: rt 0x0, rs 0x0, imm 0x000f 18440 rotr $s0, $s1, 0x03 :: rt 0x0, rs 0x0, imm 0x0003 18441 rotr $t0, $t1, 0x00 :: rt 0x9823b6e, rs 0x9823b6e, imm 0x0000 18442 rotr $t2, $t3, 0x1f :: rt 0x130476dc, rs 0x9823b6e, imm 0x001f [all …]
|
/external/llvm/lib/Target/X86/ |
D | X86InstrShiftRotate.td | 580 [(set GR8:$dst, (rotr GR8:$src1, CL))], IIC_SR>; 583 [(set GR16:$dst, (rotr GR16:$src1, CL))], IIC_SR>, OpSize16; 586 [(set GR32:$dst, (rotr GR32:$src1, CL))], IIC_SR>, OpSize32; 589 [(set GR64:$dst, (rotr GR64:$src1, CL))], IIC_SR>; 594 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))], IIC_SR>; 597 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))], 601 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))], 606 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))], 612 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))], 616 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))], [all …]
|
/external/llvm/test/MC/Mips/mips64/ |
D | invalid-mips64r2.s | 24 …rotr $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe… 25 …rotr $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
|
/external/chromium_org/v8/test/cctest/ |
D | test-disasm-mips.cc | 356 COMPARE(rotr(a0, a1, 0), in TEST() 358 COMPARE(rotr(s0, s1, 8), in TEST() 360 COMPARE(rotr(t2, t3, 24), in TEST() 362 COMPARE(rotr(v0, v1, 31), in TEST()
|
/external/openssl/crypto/sha/asm/ |
D | sha1-586.pl | 152 &rotr($b,2); # b=ROTATE(b,30) 179 &rotr($b,$n==16?2:7); # b=ROTATE(b,30) 196 &rotr($b,2); # b=ROTATE(b,30) 221 &rotr($b,7); # b=ROTATE(b,30) 229 &rotr($a,5) if ($n==79); 239 &rotr($b,2); # b=ROTATE(b,30) 264 &rotr($b,7); # b=ROTATE(b,30) 283 &rotr($b,2); # b=ROTATE(b,30)
|
/external/llvm/test/MC/Mips/mips32/ |
D | invalid-mips32r2.s | 26 …rotr $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat… 27 …rotr $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
|
/external/llvm/test/MC/Mips/mips64r2/ |
D | valid.s | 194 … rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2] 195 … rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2]
|
/external/chromium_org/third_party/boringssl/src/crypto/sha/asm/ |
D | sha1-586.pl | 169 &rotr($b,2); # b=ROTATE(b,30) 196 &rotr($b,$n==16?2:7); # b=ROTATE(b,30) 213 &rotr($b,2); # b=ROTATE(b,30) 238 &rotr($b,7); # b=ROTATE(b,30) 246 &rotr($a,5) if ($n==79); 256 &rotr($b,2); # b=ROTATE(b,30) 281 &rotr($b,7); # b=ROTATE(b,30) 300 &rotr($b,2); # b=ROTATE(b,30)
|
/external/chromium_org/third_party/boringssl/src/crypto/perlasm/ |
D | cbc.pl | 283 &rotr("edx", 16); 294 &rotr("ecx", 16);
|
/external/openssl/crypto/perlasm/ |
D | cbc.pl | 283 &rotr("edx", 16); 294 &rotr("ecx", 16);
|