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/external/llvm/test/CodeGen/PowerPC/
Dvec_cmp.ll14 %sext = sext <2 x i1> %cmp to <2 x i8>
15 ret <2 x i8> %sext
23 %sext = sext <4 x i1> %cmp to <4 x i8>
24 ret <4 x i8> %sext
32 %sext = sext <8 x i1> %cmp to <8 x i8>
33 ret <8 x i8> %sext
43 %sext = sext <16 x i1> %cmp to <16 x i8>
44 ret <16 x i8> %sext
52 %sext = sext <16 x i1> %cmp to <16 x i8>
53 ret <16 x i8> %sext
[all …]
/external/llvm/test/CodeGen/X86/
Dpmovsx-inreg.ll10 %sext = sext <2 x i8> %wide.load35 to <2 x i64>
12 store <2 x i64> %sext, <2 x i64>* %out, align 8
27 %sext = sext <4 x i8> %wide.load35 to <4 x i64>
29 store <4 x i64> %sext, <4 x i64>* %out, align 8
38 %sext = sext <4 x i8> %wide.load35 to <4 x i32>
40 store <4 x i32> %sext, <4 x i32>* %out, align 8
55 %sext = sext <8 x i8> %wide.load35 to <8 x i32>
57 store <8 x i32> %sext, <8 x i32>* %out, align 8
66 %sext = sext <8 x i8> %wide.load35 to <8 x i16>
68 store <8 x i16> %sext, <8 x i16>* %out, align 8
[all …]
Dvec_sext.ll6 %G = sext <4 x i16> %F to <4 x i32>
8 %Y = sext <4 x i16> %H to <4 x i32>
16 %G = sext <4 x i16> %F to <4 x i64>
18 %Y = sext <4 x i16> %H to <4 x i64>
26 %G = sext <4 x i32> %F to <4 x i64>
28 %Y = sext <4 x i32> %H to <4 x i64>
35 %G = sext <4 x i8> %F to <4 x i16>
37 %Y = sext <4 x i8> %H to <4 x i16>
44 %G = sext <4 x i8> %F to <4 x i32>
46 %Y = sext <4 x i8> %H to <4 x i32>
[all …]
Dcodegen-prepare-addrmode-sext.ll14 ; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i32 %arg1 to i64
15 ; CHECK: [[ARG2SEXT:%[a-zA-Z_0-9-]+]] = sext i32 %arg2 to i64
21 %sextadd = sext i32 %add to i64
30 ; (This is a heuristic of course, because the new sext could have been
37 %sextadd = sext i32 %add to i64
50 %sextadd = sext i32 %add to i64
58 ; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i32 %arg1 to i64
64 %sextadd = sext i32 %add to i64
74 ; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i8 [[ARG1TRUNC]] to i64
81 %sextadd = sext i8 %add to i64
[all …]
/external/llvm/test/CodeGen/R600/
Dsign_extend.ll8 %sext = sext i1 %cmp to i32
9 store i32 %sext, i32 addrspace(1)* %out, align 4
20 %sext = sext i32 %add to i64
21 store i64 %sext, i64 addrspace(1)* %out, align 8
31 %sext = sext i1 %cmp to i64
32 store i64 %sext, i64 addrspace(1)* %out, align 8
40 %sext = sext i32 %a to i64
41 store i64 %sext, i64 addrspace(1)* %out, align 8
50 %sext = sext i32 %val to i64
51 store i64 %sext, i64 addrspace(1)* %out, align 8
[all …]
Dsetcc64.ll14 %1 = sext i1 %0 to i32
24 %1 = sext i1 %0 to i32
34 %1 = sext i1 %0 to i32
44 %1 = sext i1 %0 to i32
54 %1 = sext i1 %0 to i32
68 %1 = sext i1 %0 to i32
78 %1 = sext i1 %0 to i32
92 %1 = sext i1 %0 to i32
106 %1 = sext i1 %0 to i32
120 %1 = sext i1 %0 to i32
[all …]
Dsetcc.ll10 %sext = sext <2 x i1> %result to <2 x i32>
11 store <2 x i32> %sext, <2 x i32> addrspace(1)* %out
26 %sext = sext <4 x i1> %result to <4 x i32>
27 store <4 x i32> %sext, <4 x i32> addrspace(1)* %out
41 %1 = sext i1 %0 to i32
52 %1 = sext i1 %0 to i32
63 %1 = sext i1 %0 to i32
74 %1 = sext i1 %0 to i32
85 %1 = sext i1 %0 to i32
105 %1 = sext i1 %0 to i32
[all …]
/external/llvm/test/Transforms/InstCombine/
Dsext.ll11 %s = sext i32 %t to i64
20 %s = sext i32 %t to i64
29 %s = sext i32 %t to i64
38 %s = sext i32 %t to i64
47 %s = sext i32 %t to i64
56 %s = sext i32 %t to i64
65 %s = sext i32 %u to i64
75 %n = sext i16 %s to i32
88 %t2 = sext i16 %t to i32
109 %b = sext i8 %a to i32
[all …]
/external/llvm/test/Analysis/Delinearization/
Dhimeno_2.ll29 …sext i32 %a.deps to i64) * (1 + (sext i32 %a.cols to i64))) + %a.base),+,(4 * (sext i32 %a.deps to…
31 ; CHECK: ArrayDecl[UnknownSize][(sext i32 %a.cols to i64)][(sext i32 %a.deps to i64)] with elements…
41 %p.rows.sext = sext i32 %p.rows.sub to i64
45 %p.cols.sext = sext i32 %p.cols.sub to i64
49 %p.deps.sext = sext i32 %p.deps.sub to i64
52 %a.cols.sext = sext i32 %a.cols to i64
55 %a.deps.sext = sext i32 %a.deps to i64
70 %tmp1 = mul nsw i64 %a.cols.sext, %i
72 %tmp3 = mul i64 %tmp2, %a.deps.sext
77 %k.exitcond = icmp eq i64 %k.inc, %p.deps.sext
[all …]
Dhimeno_1.ll29 …sext i32 %a.deps to i64) * (1 + (sext i32 %a.cols to i64))) + %a.base),+,(4 * (sext i32 %a.deps to…
31 ; CHECK: ArrayDecl[UnknownSize][(sext i32 %a.cols to i64)][(sext i32 %a.deps to i64)] with elements…
41 %p.rows.sext = sext i32 %p.rows.sub to i64
45 %p.cols.sext = sext i32 %p.cols.sub to i64
49 %p.deps.sext = sext i32 %p.deps.sub to i64
64 %a.cols.sext = sext i32 %a.cols to i64
65 %a.deps.sext = sext i32 %a.deps to i64
70 %tmp1 = mul nsw i64 %a.cols.sext, %i
72 %tmp3 = mul i64 %tmp2, %a.deps.sext
77 %k.exitcond = icmp eq i64 %k.inc, %p.deps.sext
[all …]
/external/llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/
Dsplit-gep.ll22 %idxprom = sext i32 %add to i64
29 ; We should be able to trace into sext(a + b) if a + b is non-negative
35 %1 = sext i32 %0 to i64 ; inbound sext(i + 1) = sext(i) + 1
37 ; However, inbound sext(j + -2) != sext(j) + -2, e.g., j = INT_MIN
38 %3 = sext i32 %2 to i64
45 ; CHECK: sext
49 ; We should be able to trace into sext/zext if it can be distributed to both
50 ; operands, e.g., sext (add nsw a, b) == add nsw (sext a), (sext b)
53 ; gep base, a + sext(b +nsw 1), c + zext(d +nuw 1)
55 ; gep base, a + sext(b), c + zext(d); gep ..., 1 * 32 + 1
[all …]
/external/llvm/test/Analysis/CostModel/PowerPC/
Dext.ll7 ; CHECK: cost of 1 {{.*}} sext
8 %v1 = sext i16 undef to i32
10 ; CHECK: cost of 1 {{.*}} sext
11 %v2 = sext <2 x i16> undef to <2 x i32>
13 ; CHECK: cost of 1 {{.*}} sext
14 %v3 = sext <4 x i16> undef to <4 x i32>
16 ; CHECK: cost of 112 {{.*}} sext
17 %v4 = sext <8 x i16> undef to <8 x i32>
/external/llvm/test/CodeGen/XCore/
Dsext.ll4 %2 = sext i1 %1 to i32
8 ; CHECK: sext r0, 1
12 %2 = sext i2 %1 to i32
16 ; CHECK: sext r0, 2
20 %2 = sext i8 %1 to i32
24 ; CHECK: sext r0, 8
28 %2 = sext i16 %1 to i32
32 ; CHECK: sext r0, 16
/external/llvm/test/Analysis/CostModel/X86/
Dcast.ll12 ;CHECK: cost of 2 {{.*}} sext
13 %B = sext <4 x i1> undef to <4 x i32>
20 ;CHECK-NOT: cost of 2 {{.*}} sext
21 %E = sext <8 x i1> undef to <8 x i32>
42 ;CHECK-AVX2: cost of 3 {{.*}} sext
43 ;CHECK-AVX: cost of 7 {{.*}} sext
44 %S = sext <8 x i1> %in to <8 x i32>
49 ;CHECK-AVX2: cost of 1 {{.*}} sext
50 ;CHECK-AVX: cost of 4 {{.*}} sext
51 %A2 = sext <16 x i8> undef to <16 x i16>
[all …]
/external/llvm/test/CodeGen/AArch64/
Darm64-neon-compare-instructions.ll6 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
13 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
20 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
27 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
34 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
41 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
48 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
56 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
64 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
72 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
[all …]
Dneon-compare-instructions.ll7 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
15 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
23 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
31 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
39 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
47 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
55 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
64 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
73 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
82 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
[all …]
/external/llvm/test/Transforms/IndVarSimplify/
D2009-04-14-shorten_iv_vars.ll1 ; RUN: opt < %s -indvars -S | not grep "sext"
20 %2 = sext i32 %i.0.reg2mem.0 to i64 ; <i64> [#uses=1]
24 %6 = sext i32 %i.0.reg2mem.0 to i64 ; <i64> [#uses=1]
28 %10 = sext i32 %i.0.reg2mem.0 to i64 ; <i64> [#uses=1]
35 %16 = sext i32 %15 to i64 ; <i64> [#uses=1]
40 %21 = sext i32 %20 to i64 ; <i64> [#uses=1]
44 %25 = sext i32 %13 to i64 ; <i64> [#uses=1]
51 %31 = sext i32 %30 to i64 ; <i64> [#uses=1]
56 %36 = sext i32 %35 to i64 ; <i64> [#uses=1]
60 %40 = sext i32 %28 to i64 ; <i64> [#uses=1]
[all …]
Delim-extend.ll6 ; IV rewrite only removes one sext. WidenIVs removes all three.
11 ; CHECK-NOT: sext
16 %preofs = sext i32 %iv to i64
20 %postofs = sext i32 %postiv to i64
24 %postofsnsw = sext i32 %postivnsw to i64
43 ; CHECK-NOT: sext
48 %preofs = sext i32 %iv to i64
52 %postofs = sext i32 %postiv to i64
56 %postofsnsw = sext i32 %postivnsw to i64
80 ; CHECK-NOT: sext
[all …]
/external/llvm/test/CodeGen/SystemZ/
Dint-conv-03.ll11 %ext = sext i8 %byte to i64
21 %ext = sext i8 %byte to i64
31 %ext = sext i8 %byte to i64
42 %ext = sext i8 %byte to i64
55 %ext = sext i8 %byte to i64
66 %ext = sext i8 %byte to i64
77 %ext = sext i8 %byte to i64
90 %ext = sext i8 %byte to i64
103 %ext = sext i8 %byte to i64
147 %ext0 = sext i8 %trunc0 to i64
[all …]
Dint-conv-01.ll11 %ext = sext i8 %byte to i32
21 %ext = sext i8 %byte to i32
31 %ext = sext i8 %byte to i32
42 %ext = sext i8 %byte to i32
55 %ext = sext i8 %byte to i32
66 %ext = sext i8 %byte to i32
77 %ext = sext i8 %byte to i32
90 %ext = sext i8 %byte to i32
103 %ext = sext i8 %byte to i32
147 %ext0 = sext i8 %trunc0 to i32
[all …]
Dint-conv-07.ll11 %ext = sext i16 %half to i64
21 %ext = sext i16 %half to i64
31 %ext = sext i16 %half to i64
42 %ext = sext i16 %half to i64
55 %ext = sext i16 %half to i64
66 %ext = sext i16 %half to i64
77 %ext = sext i16 %half to i64
90 %ext = sext i16 %half to i64
103 %ext = sext i16 %half to i64
147 %ext0 = sext i16 %trunc0 to i64
[all …]
Dint-conv-05.ll11 %ext = sext i16 %half to i32
21 %ext = sext i16 %half to i32
31 %ext = sext i16 %half to i32
42 %ext = sext i16 %half to i32
53 %ext = sext i16 %half to i32
64 %ext = sext i16 %half to i32
77 %ext = sext i16 %half to i32
88 %ext = sext i16 %half to i32
99 %ext = sext i16 %half to i32
112 %ext = sext i16 %half to i32
[all …]
/external/llvm/test/CodeGen/ARM/
D2012-08-23-legalize-vmull.ll19 %v0 = sext <4 x i8> %0 to <4 x i32>
32 %v0 = sext <2 x i8> %0 to <2 x i64>
45 %v0 = sext <2 x i16> %0 to <2 x i64>
60 %v0 = sext <4 x i8> %0 to <4 x i32>
63 %v2 = sext <4 x i8> %1 to <4 x i32>
76 %v0 = sext <2 x i8> %0 to <2 x i64>
79 %v2 = sext <2 x i8> %1 to <2 x i64>
92 %v0 = sext <2 x i16> %0 to <2 x i64>
95 %v2 = sext <2 x i16> %1 to <2 x i64>
110 %v0 = sext <4 x i8> %0 to <4 x i32>
[all …]
Dvshll.ll7 %sext = sext <8 x i8> %tmp1 to <8 x i16>
8 %shift = shl <8 x i16> %sext, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
16 %sext = sext <4 x i16> %tmp1 to <4 x i32>
17 %shift = shl <4 x i32> %sext, <i32 15, i32 15, i32 15, i32 15>
25 %sext = sext <2 x i32> %tmp1 to <2 x i64>
26 %shift = shl <2 x i64> %sext, <i64 31, i64 31>
63 %sext = sext <8 x i8> %tmp1 to <8 x i16>
64 %shift = shl <8 x i16> %sext, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
103 %sext = sext <4 x i16> %tmp1 to <4 x i32>
104 %shift = shl <4 x i32> %sext, <i32 17, i32 17, i32 17, i32 17>
/external/llvm/test/CodeGen/Mips/
Ddsp-patterns-cmp-vselect.ll352 %sext = sext <2 x i1> %cmp to <2 x i16>
353 %2 = bitcast <2 x i16> %sext to i32
367 %sext = sext <2 x i1> %cmp to <2 x i16>
368 %2 = bitcast <2 x i16> %sext to i32
382 %sext = sext <2 x i1> %cmp to <2 x i16>
383 %2 = bitcast <2 x i16> %sext to i32
397 %sext = sext <2 x i1> %cmp to <2 x i16>
398 %2 = bitcast <2 x i16> %sext to i32
412 %sext = sext <2 x i1> %cmp to <2 x i16>
413 %2 = bitcast <2 x i16> %sext to i32
[all …]

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