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Searched refs:spr (Results 1 – 25 of 35) sorted by relevance

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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/softpipe/
Dsp_texture.c55 struct softpipe_resource *spr) in softpipe_resource_layout() argument
57 struct pipe_resource *pt = &spr->base; in softpipe_resource_layout()
74 spr->stride[level] = util_format_get_stride(pt->format, width); in softpipe_resource_layout()
76 spr->level_offset[level] = buffer_size; in softpipe_resource_layout()
79 slices * spr->stride[level]); in softpipe_resource_layout()
86 spr->data = align_malloc(buffer_size, 16); in softpipe_resource_layout()
88 return spr->data != NULL; in softpipe_resource_layout()
97 struct softpipe_resource *spr) in softpipe_displaytarget_layout() argument
103 spr->dt = winsys->displaytarget_create(winsys, in softpipe_displaytarget_layout()
104 spr->base.bind, in softpipe_displaytarget_layout()
[all …]
/external/mesa3d/src/gallium/drivers/softpipe/
Dsp_texture.c55 struct softpipe_resource *spr) in softpipe_resource_layout() argument
57 struct pipe_resource *pt = &spr->base; in softpipe_resource_layout()
74 spr->stride[level] = util_format_get_stride(pt->format, width); in softpipe_resource_layout()
76 spr->level_offset[level] = buffer_size; in softpipe_resource_layout()
79 slices * spr->stride[level]); in softpipe_resource_layout()
86 spr->data = align_malloc(buffer_size, 16); in softpipe_resource_layout()
88 return spr->data != NULL; in softpipe_resource_layout()
97 struct softpipe_resource *spr) in softpipe_displaytarget_layout() argument
103 spr->dt = winsys->displaytarget_create(winsys, in softpipe_displaytarget_layout()
104 spr->base.bind, in softpipe_displaytarget_layout()
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/external/valgrind/main/VEX/priv/
Dguest_ppc_helpers.c97 UInt spr; in ppc32g_dirtyhelper_MFSPR_268_269() local
99 __asm__ __volatile__("mfspr %0,269" : "=b"(spr)); in ppc32g_dirtyhelper_MFSPR_268_269()
101 __asm__ __volatile__("mfspr %0,268" : "=b"(spr)); in ppc32g_dirtyhelper_MFSPR_268_269()
103 return spr; in ppc32g_dirtyhelper_MFSPR_268_269()
115 UInt spr; in ppc32g_dirtyhelper_MFSPR_287() local
116 __asm__ __volatile__("mfspr %0,287" : "=b"(spr)); in ppc32g_dirtyhelper_MFSPR_287()
117 return spr; in ppc32g_dirtyhelper_MFSPR_287()
/external/llvm/test/CodeGen/PowerPC/
Dvec_vrsave.ll3 ; RUN: not grep spr %t
/external/icu/icu4c/source/data/lang/
Dsv_FI.txt28 und{"okänt språk"}
Dnn.txt294 mul{"fleire språk"}
446 und{"ukjent språk"}
476 zxx{"utan språkleg innhald"}
607 Zxxx{"kode for språk utan skrift"}
Dsv.txt339 mul{"flera språk"}
506 und{"obestämt språk"}
541 zxx{"inget språkligt innehåll"}
704 Zxxx{"oskrivet språk"}
917 language{"språk: {0}"}
Dnb.txt339 mul{"flere språk"}
506 und{"ukjent språk"}
541 zxx{"uten språklig innhold"}
705 Zxxx{"språk uten skrift"}
/external/chromium_org/third_party/icu/source/data/lang/
Dsv_FI.txt28 und{"okänt språk"}
Dsv.txt332 Zxxx{"oskrivet språk"}
342 language{"språk: {0}"}
Dnb.txt333 Zxxx{"språk uten skrift"}
/external/mesa3d/src/mesa/drivers/dri/r200/
Dr200_tex.c351 R200_STATECHANGE( rmesa, spr ); in r200TexEnv()
353 rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] |= R200_PS_GEN_TEX_0 << unit; in r200TexEnv()
355 rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] &= ~(R200_PS_GEN_TEX_0 << unit); in r200TexEnv()
Dr200_state.c596 R200_STATECHANGE( rmesa, spr ); in r200PointParameter()
599 rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] &= in r200PointParameter()
611 rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] |= R200_PS_MULT_ATTENCONST; in r200PointParameter()
613 rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] |= R200_PS_LIN_ATT_ZERO; in r200PointParameter()
620 rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] |= in r200PointParameter()
1904 R200_STATECHANGE( rmesa, spr ); in r200Enable()
1908 rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] |= in r200Enable()
1912 rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] &= ~R200_PS_GEN_TEX_MASK; in r200Enable()
Dr200_context.h517 struct radeon_state_atom spr; member
Dr200_cmdbuf.c102 insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.spr ); in r200SetUpAtomList()
Dr200_state_init.c745 ALLOC_STATE( spr, always, SPR_STATE_SIZE, "SPR/pointsprite", 0 ); in r200InitState()
815 rmesa->hw.spr.cmd[SPR_CMD_0] = cmdpkt(rmesa, R200_EMIT_TCL_POINT_SPRITE_CNTL); in r200InitState()
1263 rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] = in r200InitState()
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/r200/
Dr200_tex.c351 R200_STATECHANGE( rmesa, spr ); in r200TexEnv()
353 rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] |= R200_PS_GEN_TEX_0 << unit; in r200TexEnv()
355 rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] &= ~(R200_PS_GEN_TEX_0 << unit); in r200TexEnv()
Dr200_state.c596 R200_STATECHANGE( rmesa, spr ); in r200PointParameter()
599 rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] &= in r200PointParameter()
611 rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] |= R200_PS_MULT_ATTENCONST; in r200PointParameter()
613 rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] |= R200_PS_LIN_ATT_ZERO; in r200PointParameter()
620 rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] |= in r200PointParameter()
1904 R200_STATECHANGE( rmesa, spr ); in r200Enable()
1908 rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] |= in r200Enable()
1912 rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] &= ~R200_PS_GEN_TEX_MASK; in r200Enable()
Dr200_context.h517 struct radeon_state_atom spr; member
Dr200_cmdbuf.c102 insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.spr ); in r200SetUpAtomList()
Dr200_state_init.c745 ALLOC_STATE( spr, always, SPR_STATE_SIZE, "SPR/pointsprite", 0 ); in r200InitState()
815 rmesa->hw.spr.cmd[SPR_CMD_0] = cmdpkt(rmesa, R200_EMIT_TCL_POINT_SPRITE_CNTL); in r200InitState()
1263 rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] = in r200InitState()
/external/openssl/crypto/des/
DImakefile18 LIBDES= des_crypt.man des.h des_locl.h podd.h sk.h spr.h
DFILES060 spr.h - What is left of the S tables - used in ecb_encrypt().
/external/eigen/blas/
Dlevel2_real_impl.h234 int EIGEN_BLAS_FUNC(spr)(char *uplo, int *n, Scalar *palpha, Scalar *px, int *incx, Scalar *pap) in EIGEN_BLAS_FUNC() argument
/external/llvm/lib/Target/PowerPC/
DPPCInstrFormats.td898 class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
901 let SPR = spr;
947 class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
950 let SPR = spr;

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