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/external/llvm/test/CodeGen/SystemZ/
Dshift-03.ll8 ; CHECK: sra %r2, 1
17 ; CHECK: sra %r2, 31
26 ; CHECK-NOT: sra %r2, 32
35 ; CHECK-NOT: sra %r2, -1{{.*}}
45 ; CHECK: sra %r2, 0(%r3)
54 ; CHECK: sra %r2, 10(%r3)
64 ; CHECK: sra %r2, 10(%r3)
76 ; CHECK: sra %r2, 4095(%r3)
87 ; CHECK: sra %r2, 0(%r3)
98 ; CHECK: sra %r2, 0({{%r[34]}})
[all …]
Dselectcc-01.ll10 ; CHECK-NEXT: sra %r2, 31
23 ; CHECK-NEXT: sra %r2, 31
35 ; CHECK-NEXT: sra %r2, 31
48 ; CHECK-NEXT: sra %r2, 31
61 ; CHECK-NEXT: sra %r2, 31
74 ; CHECK-NEXT: sra %r2, 31
86 ; CHECK-NEXT: sra %r2, 31
98 ; CHECK-NEXT: sra %r2, 31
111 ; CHECK-NEXT: sra %r2, 31
123 ; CHECK-NEXT: sra %r2, 31
[all …]
Dselectcc-02.ll10 ; CHECK-NEXT: sra %r2, 31
23 ; CHECK-NEXT: sra %r2, 31
35 ; CHECK-NEXT: sra %r2, 31
48 ; CHECK-NEXT: sra %r2, 31
60 ; CHECK-NEXT: sra %r2, 31
73 ; CHECK-NEXT: sra %r2, 31
85 ; CHECK-NEXT: sra %r2, 31
97 ; CHECK-NEXT: sra %r2, 31
110 ; CHECK-NEXT: sra %r2, 31
123 ; CHECK-NEXT: sra %r2, 31
[all …]
/external/llvm/test/MC/Mips/
Dmicromips-shift-instructions.s12 # CHECK-EL: sra $4, $3, 7 # encoding: [0x83,0x00,0x80,0x38]
23 # CHECK-EB: sra $4, $3, 7 # encoding: [0x00,0x83,0x38,0x80]
31 sra $4, $3, 7
Dmips-alu-instructions.s28 # CHECK: sra $4, $3, 7 # encoding: [0xc3,0x21,0x03,0x00]
59 sra $4, $3, 7
Dmips64-alu-instructions.s26 # CHECK: sra $4, $3, 7 # encoding: [0xc3,0x21,0x03,0x00]
54 sra $4, $3, 7
/external/llvm/test/CodeGen/Mips/msa/
Dshift-dagcombine.ll8 ; CHECK-NOT: sra
10 ; CHECK-NOT: sra
16 ; CHECK-NOT: sra
18 ; CHECK-NOT: sra
Dbasic_operations.ll271 ; MIPS32-AE-NOT: sra
290 ; MIPS32-AE-NOT: sra
325 ; MIPS32-AE-NOT: sra
419 ; MIPS32-AE-DAG: sra [[R6:\$[0-9]+]], [[R5]], 24
443 ; MIPS32-AE-DAG: sra [[R6:\$[0-9]+]], [[R5]], 16
466 ; MIPS32-AE-NOT: sra
491 ; MIPS32-AE-NOT: sra
603 ; MIPS32-AE-NOT: sra
625 ; MIPS32-AE-NOT: sra
644 ; MIPS32-AE-NOT: sra
[all …]
/external/llvm/test/MC/Mips/mips1/
Dvalid.s90 … sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
91 … sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
92 … sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
/external/llvm/test/CodeGen/X86/
Dsse2-vector-shifts.ll281 %sra = ashr <4 x i32> %x, %y
282 %srl1 = lshr <4 x i32> %sra, <i32 31, i32 31, i32 31, i32 31>
330 %sra = ashr <4 x i16> %trunc, <i16 3, i16 3, i16 3, i16 3>
331 ret <4 x i16> %sra
349 %sra = ashr <4 x i32> %x, <i32 3, i32 3, i32 3, i32 3>
350 ret <4 x i32> %sra
357 %sra = lshr <4 x i32> %x, <i32 3, i32 3, i32 3, i32 3>
358 ret <4 x i32> %sra
365 %sra = shl <4 x i32> %x, <i32 3, i32 3, i32 3, i32 3>
366 ret <4 x i32> %sra
/external/llvm/test/MC/Mips/mips2/
Dvalid.s106 … sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
107 … sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
108 … sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
/external/libunwind/src/mips/
Dgetcontext-android.S38 sra $1, $X, 31; \
43 sra $1, $31, 31; \
Dgetcontext.S39 sra $1, $X, 31; \
44 sra $1, $31, 31; \
/external/llvm/test/MC/Mips/mips32/
Dvalid.s134 … sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
135 … sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
136 … sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
/external/llvm/test/MC/Sparc/
Dsparc-alu-instructions.s60 ! CHECK: sra %g1, %g2, %g3 ! encoding: [0x87,0x38,0x40,0x02]
61 sra %g1, %g2, %g3
62 ! CHECK: sra %g1, 31, %g3 ! encoding: [0x87,0x38,0x60,0x1f]
63 sra %g1, 31, %g3
/external/valgrind/main/none/tests/mips64/
Dshift_instructions.stdout.exp-mips6416385 sra $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000
16386 sra $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f
16387 sra $a0, $a1, 0x0f :: rt 0x0, rs 0x0, imm 0x000f
16388 sra $s0, $s1, 0x03 :: rt 0x0, rs 0x0, imm 0x0003
16389 sra $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000
16390 sra $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f
16391 sra $a0, $a1, 0x0f :: rt 0x0, rs 0x0, imm 0x000f
16392 sra $s0, $s1, 0x03 :: rt 0x0, rs 0x0, imm 0x0003
16393 sra $t0, $t1, 0x00 :: rt 0x9823b6e, rs 0x9823b6e, imm 0x0000
16394 sra $t2, $t3, 0x1f :: rt 0x0, rs 0x9823b6e, imm 0x001f
[all …]
Dshift_instructions.stdout.exp-mips64r222273 sra $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000
22274 sra $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f
22275 sra $a0, $a1, 0x0f :: rt 0x0, rs 0x0, imm 0x000f
22276 sra $s0, $s1, 0x03 :: rt 0x0, rs 0x0, imm 0x0003
22277 sra $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000
22278 sra $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f
22279 sra $a0, $a1, 0x0f :: rt 0x0, rs 0x0, imm 0x000f
22280 sra $s0, $s1, 0x03 :: rt 0x0, rs 0x0, imm 0x0003
22281 sra $t0, $t1, 0x00 :: rt 0x9823b6e, rs 0x9823b6e, imm 0x0000
22282 sra $t2, $t3, 0x1f :: rt 0x0, rs 0x9823b6e, imm 0x001f
[all …]
/external/llvm/test/MC/Mips/mips32r2/
Dvalid.s162 … sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
163 … sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
164 … sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
/external/llvm/test/MC/Mips/mips3/
Dvalid.s164 … sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
165 … sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
166 … sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
/external/llvm/test/CodeGen/Mips/
Dmadd-msub.ll14 ; 32-DAG: sra $[[T0:[0-9]+]], $6, 31
20 ; DSP-DAG: sra $[[T0:[0-9]+]], $6, 31
29 ; 32R6-DAG: sra $[[T3:[0-9]+]], $6, 31
151 ; 32-DAG: sra $[[T0:[0-9]+]], $6, 31
157 ; DSP-DAG: sra $[[T0:[0-9]+]], $6, 31
167 ; 32R6-DAG: sra $[[T5:[0-9]+]], $6, 31
/external/llvm/test/MC/Mips/mips4/
Dvalid.s182 … sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
183 … sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
184 … sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
/external/llvm/test/MC/Mips/mips5/
Dvalid.s183 … sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
184 … sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
185 … sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
/external/chromium_org/courgette/
DOWNERS2 sra@chromium.org
/external/llvm/lib/Target/X86/
DX86InstrShiftRotate.td228 [(set GR8:$dst, (sra GR8:$src1, CL))],
232 [(set GR16:$dst, (sra GR16:$src1, CL))],
236 [(set GR32:$dst, (sra GR32:$src1, CL))],
240 [(set GR64:$dst, (sra GR64:$src1, CL))],
246 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))],
250 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))],
254 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))],
259 [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))],
265 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))],
269 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))],
[all …]
/external/llvm/test/MC/Mips/mips64/
Dvalid.s199 … sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
200 … sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
201 … sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]

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