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/external/llvm/lib/Target/Hexagon/
DHexagonIntrinsicsV5.td2 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1),
3 !strconcat("$dst = ", !strconcat(opc , "($src1)")),
4 [(set IntRegs:$dst, (IntID IntRegs:$src1))]>;
7 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1),
8 !strconcat("$dst = ", !strconcat(opc , "($src1)")),
9 [(set IntRegs:$dst, (IntID IntRegs:$src1))]>;
12 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1),
13 !strconcat("$dst = ", !strconcat(opc , "($src1)")),
14 [(set IntRegs:$dst, (IntID IntRegs:$src1))]>;
17 : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1),
[all …]
DHexagonInstrInfoV5.td14 def CONST64_Float_Real : LDInst<(outs DoubleRegs:$dst), (ins f64imm:$src1),
15 "$dst = CONST64(#$src1)",
16 [(set DoubleRegs:$dst, fpimm:$src1)]>,
20 def CONST32_Float_Real : LDInst<(outs IntRegs:$dst), (ins f32imm:$src1),
21 "$dst = CONST32(#$src1)",
22 [(set IntRegs:$dst, fpimm:$src1)]>,
34 def TFRI_f : ALU32_ri<(outs IntRegs:$dst), (ins f32Ext:$src1),
35 "$dst = #$src1",
36 [(set IntRegs:$dst, fpimm:$src1)]>,
42 (ins PredRegs:$src1, f32Ext:$src2),
[all …]
DHexagonIntrinsics.td21 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
22 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
23 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
26 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s10Imm:$src2),
27 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
28 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
31 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2),
32 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
33 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
36 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u8Imm:$src2),
[all …]
DHexagonInstrInfo.td99 (ins PredRegs:$src1, IntRegs:$src2, IntRegs: $src3),
100 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
118 (ins IntRegs:$src1, IntRegs:$src2),
119 "$dst = "#mnemonic#"($src1, $src2)",
120 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
142 (ins IntRegs:$src1, IntRegs:$src2),
143 "$dst = combine($src1, $src2)",
145 (i64 (HexagonWrapperCombineRR (i32 IntRegs:$src1),
162 ALU32_ii<(outs DoubleRegs:$dst), (ins imm1:$src1, imm2:$src2),
163 "$dst = combine(#$src1, #$src2)",
[all …]
DHexagonIntrinsicsV4.td21 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
22 !strconcat("$dst = ", !strconcat(opc , "($src1, ~$src2)")),
23 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
26 : ALU32_rr<(outs DoubleRegs:$dst), (ins s8Imm:$src1, IntRegs:$src2),
27 !strconcat("$dst = ", !strconcat(opc , "(#$src1, $src2)")),
28 [(set DoubleRegs:$dst, (IntID imm:$src1, IntRegs:$src2))]>;
31 : ALU32_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2),
32 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
33 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
36 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
[all …]
/external/qemu/target-i386/
Dcc_helper_template.h58 target_long src1, src2; in glue() local
59 src1 = CC_SRC; in glue()
61 cf = (DATA_TYPE)CC_DST < (DATA_TYPE)src1; in glue()
63 af = (CC_DST ^ src1 ^ src2) & 0x10; in glue()
66 of = lshift((src1 ^ src2 ^ -1) & (src1 ^ CC_DST), 12 - DATA_BITS) & CC_O; in glue()
73 target_long src1; in glue() local
74 src1 = CC_SRC; in glue()
75 cf = (DATA_TYPE)CC_DST < (DATA_TYPE)src1; in glue()
82 target_long src1, src2; in glue() local
83 src1 = CC_SRC; in glue()
[all …]
/external/opencv/cxcore/src/
Dcxcmp.cpp57 worktype a1 = _toggle_macro_(src1[x]), \
67 worktype a1 = _toggle_macro_(src1[x*2]), \
70 a1 = _toggle_macro_(src1[x*2+1]); \
81 worktype a1 = _toggle_macro_(src1[x*3]), \
84 a1 = _toggle_macro_(src1[x*3+1]); \
88 a1 = _toggle_macro_(src1[x*3+2]); \
99 worktype a1 = _toggle_macro_(src1[x*4]), \
102 a1 = _toggle_macro_(src1[x*4+1]); \
106 a1 = _toggle_macro_(src1[x*4+2]); \
110 a1 = _toggle_macro_(src1[x*4+3]); \
[all …]
/external/llvm/lib/Target/X86/
DX86InstrXOP.td83 (ins VR128:$src1, VR128:$src2),
84 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
85 [(set VR128:$dst, (Int VR128:$src1, VR128:$src2))]>, XOP_4VOp3;
87 (ins VR128:$src1, i128mem:$src2),
88 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
90 (Int VR128:$src1, (bitconvert (memopv2i64 addr:$src2))))]>,
93 (ins i128mem:$src1, VR128:$src2),
94 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
96 (Int (bitconvert (memopv2i64 addr:$src1)), VR128:$src2))]>,
115 (ins VR128:$src1, i8imm:$src2),
[all …]
DX86InstrFMA.td18 let Constraints = "$src1 = $dst" in {
26 (ins VR128:$src1, VR128:$src2, VR128:$src3),
30 VR128:$src1, VR128:$src3)))]>;
34 (ins VR128:$src1, VR128:$src2, f128mem:$src3),
37 [(set VR128:$dst, (OpVT128 (Op VR128:$src2, VR128:$src1,
42 (ins VR256:$src1, VR256:$src2, VR256:$src3),
45 [(set VR256:$dst, (OpVT256 (Op VR256:$src2, VR256:$src1,
50 (ins VR256:$src1, VR256:$src2, f256mem:$src3),
54 (OpVT256 (Op VR256:$src2, VR256:$src1,
57 } // Constraints = "$src1 = $dst"
[all …]
DX86InstrAVX512.td105 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
106 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
110 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
111 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
118 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
119 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
123 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
124 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
130 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
131 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
[all …]
/external/llvm/test/CodeGen/SystemZ/
Dint-cmp-38.ll10 define i32 @f1(i32 %src1) {
17 %cond = icmp slt i32 %src1, %src2
20 %mul = mul i32 %src1, %src1
23 %res = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
28 define i32 @f2(i32 %src1) {
35 %cond = icmp ult i32 %src1, %src2
38 %mul = mul i32 %src1, %src1
41 %res = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
46 define i32 @f3(i32 %src1) {
53 %cond = icmp eq i32 %src1, %src2
[all …]
Dint-cmp-42.ll10 define i64 @f1(i64 %src1) {
18 %cond = icmp ult i64 %src1, %src2
21 %mul = mul i64 %src1, %src1
24 %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
29 define i64 @f2(i64 %src1) {
36 %cond = icmp slt i64 %src1, %src2
39 %mul = mul i64 %src1, %src1
42 %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
47 define i64 @f3(i64 %src1) {
55 %cond = icmp eq i64 %src1, %src2
[all …]
Dint-cmp-43.ll10 define i64 @f1(i64 %src1) {
17 %cond = icmp slt i64 %src1, %src2
20 %mul = mul i64 %src1, %src1
23 %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
28 define i64 @f2(i64 %src1) {
35 %cond = icmp ult i64 %src1, %src2
38 %mul = mul i64 %src1, %src1
41 %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
46 define i64 @f3(i64 %src1) {
53 %cond = icmp eq i64 %src1, %src2
[all …]
Dint-cmp-37.ll10 define i32 @f1(i32 %src1) {
18 %cond = icmp ult i32 %src1, %src2
21 %mul = mul i32 %src1, %src1
24 %res = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
29 define i32 @f2(i32 %src1) {
36 %cond = icmp slt i32 %src1, %src2
39 %mul = mul i32 %src1, %src1
42 %res = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
47 define i32 @f3(i32 %src1) {
55 %cond = icmp eq i32 %src1, %src2
[all …]
Dint-cmp-41.ll10 define i64 @f1(i64 %src1) {
18 %cond = icmp slt i64 %src1, %src2
21 %mul = mul i64 %src1, %src1
24 %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
29 define i64 @f2(i64 %src1) {
36 %cond = icmp ult i64 %src1, %src2
39 %mul = mul i64 %src1, %src1
42 %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
47 define i64 @f3(i64 %src1) {
55 %cond = icmp eq i64 %src1, %src2
[all …]
Dint-cmp-39.ll10 define i64 @f1(i64 %src1) {
18 %cond = icmp slt i64 %src1, %src2
21 %mul = mul i64 %src1, %src1
24 %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
29 define i64 @f2(i64 %src1) {
36 %cond = icmp ult i64 %src1, %src2
39 %mul = mul i64 %src1, %src1
42 %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
47 define i64 @f3(i64 %src1) {
55 %cond = icmp eq i64 %src1, %src2
[all …]
Dint-cmp-36.ll10 define i32 @f1(i32 %src1) {
18 %cond = icmp slt i32 %src1, %src2
21 %mul = mul i32 %src1, %src1
24 %res = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
29 define i32 @f2(i32 %src1) {
36 %cond = icmp ult i32 %src1, %src2
39 %mul = mul i32 %src1, %src1
42 %res = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
47 define i32 @f3(i32 %src1) {
55 %cond = icmp eq i32 %src1, %src2
[all …]
Dint-cmp-40.ll10 define i64 @f1(i64 %src1) {
18 %cond = icmp ult i64 %src1, %src2
21 %mul = mul i64 %src1, %src1
24 %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
29 define i64 @f2(i64 %src1) {
36 %cond = icmp slt i64 %src1, %src2
39 %mul = mul i64 %src1, %src1
42 %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
47 define i64 @f3(i64 %src1) {
55 %cond = icmp eq i64 %src1, %src2
[all …]
/external/pcre/dist/sljit/
DsljitNativePPC_32.c45 sljit_si dst, sljit_si src1, sljit_si src2) in emit_single_op() argument
52 SLJIT_ASSERT(src1 == TMP_REG1); in emit_single_op()
59 SLJIT_ASSERT(src1 == TMP_REG1); in emit_single_op()
74 SLJIT_ASSERT(src1 == TMP_REG1); in emit_single_op()
86 SLJIT_ASSERT(src1 == TMP_REG1); in emit_single_op()
90 SLJIT_ASSERT(src1 == TMP_REG1); in emit_single_op()
94 SLJIT_ASSERT(src1 == TMP_REG1); in emit_single_op()
101 return push_inst(compiler, ADDI | D(dst) | A(src1) | compiler->imm); in emit_single_op()
106 return push_inst(compiler, ADDIS | D(dst) | A(src1) | compiler->imm); in emit_single_op()
110 return push_inst(compiler, ADDIC | D(dst) | A(src1) | compiler->imm); in emit_single_op()
[all …]
DsljitNativePPC_64.c133 FAIL_IF(push_inst(compiler, EXTSW | S(src1) | A(TMP_REG1))); \
134 src1 = TMP_REG1; \
144 FAIL_IF(push_inst(compiler, EXTSW | S(src1) | A(TMP_REG1))); \
145 src1 = TMP_REG1; \
149 sljit_si dst, sljit_si src1, sljit_si src2) in emit_single_op() argument
154 SLJIT_ASSERT(src1 == TMP_REG1); in emit_single_op()
161 SLJIT_ASSERT(src1 == TMP_REG1); in emit_single_op()
174 SLJIT_ASSERT(src1 == TMP_REG1); in emit_single_op()
189 SLJIT_ASSERT(src1 == TMP_REG1); in emit_single_op()
201 SLJIT_ASSERT(src1 == TMP_REG1); in emit_single_op()
[all …]
/external/qemu/target-arm/
Dneon_helper.c159 #define NEON_USAT(dest, src1, src2, type) do { \ argument
160 uint32_t tmp = (uint32_t)src1 + (uint32_t)src2; \
167 #define NEON_FN(dest, src1, src2) NEON_USAT(dest, src1, src2, uint8_t) argument
170 #define NEON_FN(dest, src1, src2) NEON_USAT(dest, src1, src2, uint16_t) argument
185 uint64_t HELPER(neon_qadd_u64)(CPUARMState *env, uint64_t src1, uint64_t src2) in HELPER()
189 res = src1 + src2; in HELPER()
190 if (res < src1) { in HELPER()
197 #define NEON_SSAT(dest, src1, src2, type) do { \ argument
198 int32_t tmp = (uint32_t)src1 + (uint32_t)src2; \
209 #define NEON_FN(dest, src1, src2) NEON_SSAT(dest, src1, src2, int8_t) argument
[all …]
/external/qemu/include/qemu/
Dbitmap.h128 static inline int bitmap_and(unsigned long *dst, const unsigned long *src1, in bitmap_and() argument
132 return (*dst = *src1 & *src2) != 0; in bitmap_and()
134 return slow_bitmap_and(dst, src1, src2, nbits); in bitmap_and()
137 static inline void bitmap_or(unsigned long *dst, const unsigned long *src1, in bitmap_or() argument
141 *dst = *src1 | *src2; in bitmap_or()
143 slow_bitmap_or(dst, src1, src2, nbits); in bitmap_or()
147 static inline void bitmap_xor(unsigned long *dst, const unsigned long *src1, in bitmap_xor() argument
151 *dst = *src1 ^ *src2; in bitmap_xor()
153 slow_bitmap_xor(dst, src1, src2, nbits); in bitmap_xor()
157 static inline int bitmap_andnot(unsigned long *dst, const unsigned long *src1, in bitmap_andnot() argument
[all …]
/external/llvm/test/CodeGen/X86/
Davx-unpack.ll4 define <8 x float> @unpackhips(<8 x float> %src1, <8 x float> %src2) nounwind uwtable readnone ssp {
6 …%shuffle.i = shufflevector <8 x float> %src1, <8 x float> %src2, <8 x i32> <i32 2, i32 10, i32 3, …
11 define <4 x double> @unpackhipd(<4 x double> %src1, <4 x double> %src2) nounwind uwtable readnone s…
13 …%shuffle.i = shufflevector <4 x double> %src1, <4 x double> %src2, <4 x i32> <i32 1, i32 5, i32 3,…
18 define <8 x float> @unpacklops(<8 x float> %src1, <8 x float> %src2) nounwind uwtable readnone ssp {
20 …%shuffle.i = shufflevector <8 x float> %src1, <8 x float> %src2, <8 x i32> <i32 0, i32 8, i32 1, i…
25 define <4 x double> @unpacklopd(<4 x double> %src1, <4 x double> %src2) nounwind uwtable readnone s…
27 …%shuffle.i = shufflevector <4 x double> %src1, <4 x double> %src2, <4 x i32> <i32 0, i32 4, i32 2,…
32 define <8 x float> @unpacklops-not(<8 x float> %src1, <8 x float> %src2) nounwind uwtable readnone …
34 …%shuffle.i = shufflevector <8 x float> %src1, <8 x float> %src2, <8 x i32> <i32 0, i32 8, i32 1, i…
[all …]
Davx2-unpack.ll4 define <8 x i32> @unpackhidq1(<8 x i32> %src1, <8 x i32> %src2) nounwind uwtable readnone ssp {
6 …%shuffle.i = shufflevector <8 x i32> %src1, <8 x i32> %src2, <8 x i32> <i32 2, i32 10, i32 3, i32 …
11 define <4 x i64> @unpackhiqdq1(<4 x i64> %src1, <4 x i64> %src2) nounwind uwtable readnone ssp {
13 …%shuffle.i = shufflevector <4 x i64> %src1, <4 x i64> %src2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
18 define <8 x i32> @unpacklodq1(<8 x i32> %src1, <8 x i32> %src2) nounwind uwtable readnone ssp {
20 …%shuffle.i = shufflevector <8 x i32> %src1, <8 x i32> %src2, <8 x i32> <i32 0, i32 8, i32 1, i32 9…
25 define <4 x i64> @unpacklqdq1(<4 x i64> %src1, <4 x i64> %src2) nounwind uwtable readnone ssp {
27 …%shuffle.i = shufflevector <4 x i64> %src1, <4 x i64> %src2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
32 define <16 x i16> @unpackhwd(<16 x i16> %src1, <16 x i16> %src2) nounwind uwtable readnone ssp {
34 …%shuffle.i = shufflevector <16 x i16> %src1, <16 x i16> %src2, <16 x i32> <i32 4, i32 20, i32 5, i…
[all …]
/external/chromium_org/third_party/angle/src/libGLESv2/renderer/
Dimageformats.h40 static void average(L8 *dst, const L8 *src1, const L8 *src2) in average()
42 dst->L = gl::average(src1->L, src2->L); in average()
76 static void average(R8 *dst, const R8 *src1, const R8 *src2) in average()
78 dst->R = gl::average(src1->R, src2->R); in average()
99 static void average(A8 *dst, const A8 *src1, const A8 *src2) in average()
101 dst->A = gl::average(src1->A, src2->A); in average()
125 static void average(L8A8 *dst, const L8A8 *src1, const L8A8 *src2) in average()
127 …igned short*)dst = (((*(unsigned short*)src1 ^ *(unsigned short*)src2) & 0xFEFE) >> 1) + (*(unsign… in average()
151 static void average(A8L8 *dst, const A8L8 *src1, const A8L8 *src2) in average()
153 …igned short*)dst = (((*(unsigned short*)src1 ^ *(unsigned short*)src2) & 0xFEFE) >> 1) + (*(unsign… in average()
[all …]

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