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Searched refs:srlv (Results 1 – 25 of 45) sorted by relevance

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/external/llvm/test/MC/Mips/
Dmicromips-shift-instructions.s15 # CHECK-EL: srlv $2, $3, $5 # encoding: [0x65,0x00,0x50,0x10]
26 # CHECK-EB: srlv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x50]
34 srlv $2, $3, $5
Dmips-alu-instructions.s31 # CHECK: srlv $2, $3, $5 # encoding: [0x06,0x10,0xa3,0x00]
62 srlv $2, $3, $5
Dmips64-alu-instructions.s29 # CHECK: srlv $2, $3, $5 # encoding: [0x06,0x10,0xa3,0x00]
57 srlv $2, $3, $5
/external/valgrind/main/none/tests/mips32/
DMIPS32int.stdout.exp-mips32-LE923 srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0xffffffff
924 srlv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xee00ee00
925 srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
926 srlv $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
927 srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
928 srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
929 srlv $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0xffffffff
930 srlv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
931 srlv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000
932 srlv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
[all …]
DMIPS32int.stdout.exp-mips32-BE923 srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0xffffffff
924 srlv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xee00ee00
925 srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
926 srlv $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
927 srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
928 srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
929 srlv $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0xffffffff
930 srlv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
931 srlv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000
932 srlv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
[all …]
DMIPS32int.stdout.exp-mips32r2-BE1401 srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0xffffffff
1402 srlv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xee00ee00
1403 srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
1404 srlv $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
1405 srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
1406 srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
1407 srlv $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0xffffffff
1408 srlv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
1409 srlv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000
1410 srlv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
[all …]
DMIPS32int.stdout.exp-mips32r2-LE1401 srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0xffffffff
1402 srlv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xee00ee00
1403 srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
1404 srlv $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
1405 srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
1406 srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
1407 srlv $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0xffffffff
1408 srlv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
1409 srlv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000
1410 srlv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
[all …]
/external/llvm/test/MC/Mips/mips1/
Dvalid.s96 … srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
97 … srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
/external/llvm/test/MC/Mips/mips2/
Dvalid.s112 … srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
113 … srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
/external/chromium_org/v8/test/cctest/
Dtest-disasm-mips.cc328 COMPARE(srlv(a0, a1, a2), in TEST()
330 COMPARE(srlv(s0, s1, s2), in TEST()
332 COMPARE(srlv(t2, t3, t4), in TEST()
334 COMPARE(srlv(v0, v1, fp), in TEST()
Dtest-disasm-mips64.cc441 COMPARE(srlv(a0, a1, a2), in TEST()
443 COMPARE(srlv(s0, s1, s2), in TEST()
445 COMPARE(srlv(a6, a7, t0), in TEST()
447 COMPARE(srlv(v0, v1, fp), in TEST()
/external/llvm/test/MC/Mips/mips32/
Dvalid.s140 … srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
141 … srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
/external/llvm/test/CodeGen/Mips/
Dsrl2.ll13 ; 16: srlv ${{[0-9]+}}, ${{[0-9]+}}
Datomic.ll126 ; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
165 ; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
205 ; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
243 ; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
287 ; ALL: srlv $[[R17:[0-9]+]], $[[R14]], $[[R5]]
329 ; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
/external/llvm/test/MC/Mips/mips32r2/
Dvalid.s168 … srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
169 … srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
/external/llvm/test/MC/Mips/mips3/
Dvalid.s170 … srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
171 … srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
/external/llvm/test/MC/Mips/mips4/
Dvalid.s188 … srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
189 … srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
/external/llvm/test/MC/Mips/mips5/
Dvalid.s189 … srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
190 … srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
/external/llvm/test/MC/Mips/mips64/
Dvalid.s205 … srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
206 … srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
/external/llvm/test/MC/Mips/mips64r2/
Dvalid.s232 … srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
233 … srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
/external/valgrind/main/none/tests/mips64/
Dshift_instructions.stdout.exp-mips6418689 srlv $t0, $t1, $t2 :: rd 0x0, rs 0x0, rt 0xffffffffb1f740b4
18690 srlv $t0, $t1, $t2 :: rd 0x0, rs 0x0, rt 0xffffffffb5365d03
18691 srlv $t0, $t1, $t2 :: rd 0x2, rs 0x9823b6e, rt 0xffffffffb8757bda
18692 srlv $t0, $t1, $t2 :: rd 0x6a19, rs 0xd4326d9, rt 0xffffffffbcb4666d
18693 srlv $t0, $t1, $t2 :: rd 0x130476, rs 0x130476dc, rt 0xffffffffa2f33668
18694 srlv $t0, $t1, $t2 :: rd 0x0, rs 0x17c56b6b, rt 0xffffffffa6322bdf
18695 srlv $t0, $t1, $t2 :: rd 0x6a1936, rs 0x1a864db2, rt 0xffffffffab710d06
18696 srlv $t0, $t1, $t2 :: rd 0xf23, rs 0x1e475005, rt 0xffffffffafb010b1
18697 srlv $t0, $t1, $t2 :: rd 0x2608e, rs 0x2608edb8, rt 0xffffffff97ffad0c
18698 srlv $t0, $t1, $t2 :: rd 0x4, rs 0x22c9f00f, rt 0xffffffff933eb0bb
[all …]
Dshift_instructions.stdout.exp-mips64r224577 srlv $t0, $t1, $t2 :: rd 0x0, rs 0x0, rt 0xffffffffb1f740b4
24578 srlv $t0, $t1, $t2 :: rd 0x0, rs 0x0, rt 0xffffffffb5365d03
24579 srlv $t0, $t1, $t2 :: rd 0x2, rs 0x9823b6e, rt 0xffffffffb8757bda
24580 srlv $t0, $t1, $t2 :: rd 0x6a19, rs 0xd4326d9, rt 0xffffffffbcb4666d
24581 srlv $t0, $t1, $t2 :: rd 0x130476, rs 0x130476dc, rt 0xffffffffa2f33668
24582 srlv $t0, $t1, $t2 :: rd 0x0, rs 0x17c56b6b, rt 0xffffffffa6322bdf
24583 srlv $t0, $t1, $t2 :: rd 0x6a1936, rs 0x1a864db2, rt 0xffffffffab710d06
24584 srlv $t0, $t1, $t2 :: rd 0xf23, rs 0x1e475005, rt 0xffffffffafb010b1
24585 srlv $t0, $t1, $t2 :: rd 0x2608e, rs 0x2608edb8, rt 0xffffffff97ffad0c
24586 srlv $t0, $t1, $t2 :: rd 0x4, rs 0x22c9f00f, rt 0xffffffff933eb0bb
[all …]
/external/llvm/test/MC/Disassembler/Mips/
Dmicromips.txt115 # CHECK: srlv $2, $3, $5
Dmicromips_le.txt115 # CHECK: srlv $2, $3, $5
Dmips32r2.txt401 # CHECK: srlv $2, $3, $5

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