Searched refs:sub8 (Results 1 – 17 of 17) sorted by relevance
| /external/llvm/test/CodeGen/X86/ |
| D | atom-cmpb.ll | 28 %sub8 = sub i8 %x5, %x4
32 %res = phi i8 [ %sub7, %if.then3 ], [ %sub8, %if.else ]
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| D | pr20020.ll | 50 %sub8 = fsub double %4, %5
51 %add10 = fadd double %sub, %sub8
52 %call = tail call double @sqrt(double %sub8) #2
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| D | haddsub-2.ll | 67 %sub8 = fsub float %vecext6, %vecext7
68 %vecinit9 = insertelement <4 x float> %vecinit5, float %sub8, i32 2
91 %sub8 = fsub float %vecext6, %vecext7
92 %vecinit9 = insertelement <4 x float> %vecinit5, float %sub8, i32 3
169 %sub8 = sub i32 %vecext6, %vecext7
170 %vecinit9 = insertelement <4 x i32> %vecinit5, i32 %sub8, i32 2
196 %sub8 = sub i32 %vecext6, %vecext7
197 %vecinit9 = insertelement <4 x i32> %vecinit5, i32 %sub8, i32 3
318 %sub8 = fsub double %vecext6, %vecext7
319 %vecinit9 = insertelement <4 x double> %vecinit5, double %sub8, i32 2
[all …]
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| D | atomic_add.ll | 120 define void @sub8(i64* nocapture %p) nounwind ssp {
122 ; CHECK-LABEL: sub8:
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| /external/llvm/test/Transforms/Reassociate/ |
| D | pr12245.ll | 37 %sub8 = sub nsw i32 %dec7, %9
38 store i32 %sub8, i32* @d, align 4
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| /external/llvm/lib/Target/R600/ |
| D | AMDGPURegisterInfo.cpp | 52 AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, AMDGPU::sub8, AMDGPU::sub9, in getSubRegFromChannel()
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| D | SIRegisterInfo.td | 79 sub8, sub9, sub10, sub11, sub12, sub13, sub14, sub15],
132 sub8, sub9, sub10, sub11, sub12, sub13, sub14, sub15],
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| D | SIInstrInfo.cpp | 49 AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11, in copyPhysReg()
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| /external/llvm/test/CodeGen/SystemZ/ |
| D | fp-sub-01.ll | 114 %sub8 = fsub float %sub7, %val8
115 %sub9 = fsub float %sub8, %val9
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| D | fp-sub-02.ll | 114 %sub8 = fsub double %sub7, %val8
115 %sub9 = fsub double %sub8, %val9
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| D | int-sub-04.ll | 136 %sub8 = sub i64 %sub7, %val8
137 %sub9 = sub i64 %sub8, %val9
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| D | int-sub-01.ll | 171 %sub8 = sub i32 %sub7, %val8
172 %sub9 = sub i32 %sub8, %val9
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| D | int-sub-02.ll | 176 %sub8 = sub i64 %sub7, %ext8
177 %sub9 = sub i64 %sub8, %ext9
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| D | int-sub-03.ll | 176 %sub8 = sub i64 %sub7, %ext8
177 %sub9 = sub i64 %sub8, %ext9
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| /external/qemu/target-arm/ |
| D | op_addsub.h | 58 uint32_t HELPER(glue(PFX,sub8))(uint32_t a, uint32_t b GE_ARG) in HELPER() argument
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| D | helper.h | 20 DEF_HELPER_3(pfx ## sub8, i32, i32, i32, ptr) \
32 DEF_HELPER_2(pfx ## sub8, i32, i32, i32) \
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| D | translate.c | 515 case 7: gen_pas_helper(glue(pfx,sub8)); break; \
560 case 4: gen_pas_helper(glue(pfx,sub8)); break; \
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