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Searched refs:target_ulong (Results 1 – 25 of 57) sorted by relevance

123

/external/qemu/target-mips/
Dcpu.h32 target_ulong VPN;
42 target_ulong PFN[2];
49 …int (*map_address) (struct CPUMIPSState *env, hwaddr *physical, int *prot, target_ulong address, i…
149 target_ulong gpr[32];
150 target_ulong PC;
151 target_ulong HI[MIPS_DSP_ACC];
152 target_ulong LO[MIPS_DSP_ACC];
153 target_ulong ACX[MIPS_DSP_ACC];
154 target_ulong DSPControl;
173 target_ulong CP0_TCHalt;
[all …]
Dop_helper.c128 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
135 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
156 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \ in HELPER_LD()
163 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
182 target_ulong helper_clo (target_ulong arg1)
187 target_ulong helper_clz (target_ulong arg1) in helper_clz()
193 target_ulong helper_dclo (target_ulong arg1) in helper_dclo()
198 target_ulong helper_dclz (target_ulong arg1) in helper_dclz()
216 static inline void set_HIT0_LO (CPUMIPSState *env, target_ulong arg1, uint64_t HILO) in set_HIT0_LO()
222 static inline void set_HI_LOT0 (CPUMIPSState *env, target_ulong arg1, uint64_t HILO) in set_HI_LOT0()
[all …]
Dhelper.c38 target_ulong address, int rw, int access_type) in no_mmu_map_address()
47 target_ulong address, int rw, int access_type) in fixed_mmu_map_address()
65 target_ulong address, int rw, int access_type) in r4k_map_address()
69 target_ulong mask; in r4k_map_address()
70 target_ulong tag; in r4k_map_address()
71 target_ulong VPN; in r4k_map_address()
108 int *prot, target_ulong address, in get_physical_address()
209 static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, in raise_mmu_exception()
267 target_ulong pgd_current_p;
271 static inline target_ulong cpu_mips_get_pgd(CPUMIPSState *env) in cpu_mips_get_pgd()
[all …]
/external/qemu/include/exec/
Dcpu-defs.h44 typedef uint32_t target_ulong; typedef
50 typedef uint64_t target_ulong; typedef
93 target_ulong addr_read;
94 target_ulong addr_write;
95 target_ulong addr_code;
101 (sizeof(target_ulong) * 3 +
102 ((-sizeof(target_ulong) * 3) & (sizeof(uintptr_t) - 1)) +
112 target_ulong tlb_flush_addr; \
113 target_ulong tlb_flush_mask;
139 target_ulong pc;
[all …]
Dexec-all.h92 target_ulong pc, target_ulong cs_base, int flags,
96 int page_unprotect(target_ulong address, uintptr_t pc, void *puc);
103 void tlb_flush_page(CPUArchState *env, target_ulong addr);
105 void tlb_set_page(CPUArchState *env, target_ulong vaddr,
107 int mmu_idx, target_ulong size);
111 static inline void tlb_flush_page(CPUArchState *env, target_ulong addr) in tlb_flush_page()
153 target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
154 target_ulong cs_base; /* CS base for this block */
206 static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc) in tb_jmp_cache_hash_page()
208 target_ulong tmp; in tb_jmp_cache_hash_page()
[all …]
Dcputlb.h26 target_ulong vaddr);
30 void tlb_set_dirty(CPUArchState *env, target_ulong vaddr);
34 void tb_flush_jmp_cache(CPUArchState *env, target_ulong addr);
42 target_ulong vaddr,
45 target_ulong *address);
Dsoftmmu_header.h84 glue(glue(cpu_ld, USUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr) in glue()
88 target_ulong addr; in glue()
106 glue(glue(cpu_lds, SUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr) in glue()
109 target_ulong addr; in glue()
132 glue(glue(cpu_st, SUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr, in glue()
136 target_ulong addr; in glue()
157 target_ulong ptr) in glue()
168 target_ulong ptr, float64 v) in glue()
181 target_ulong ptr) in glue()
192 target_ulong ptr, float32 v) in glue()
Dsoftmmu_template.h117 target_ulong addr, in glue()
147 WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx, in helper_le_ld_name()
151 target_ulong tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ; in helper_le_ld_name()
189 target_ulong addr1, addr2; in helper_le_ld_name()
229 WORD_TYPE helper_be_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx, in helper_be_ld_name()
233 target_ulong tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ; in helper_be_ld_name()
271 target_ulong addr1, addr2; in helper_be_ld_name()
305 glue(glue(helper_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr, in glue()
316 WORD_TYPE helper_le_lds_name(CPUArchState *env, target_ulong addr, in helper_le_lds_name()
323 WORD_TYPE helper_be_lds_name(CPUArchState *env, target_ulong addr, in helper_be_lds_name()
[all …]
Dcpu-all.h202 #define g2h(x) ((void *)((unsigned long)(target_ulong)(x) + GUEST_BASE))
359 int page_get_flags(target_ulong address);
360 void page_set_flags(target_ulong start, target_ulong end, int flags);
361 int page_check_range(target_ulong start, target_ulong len, int flags);
426 int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags,
428 int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags);
431 int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len,
433 int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr,
434 target_ulong len, int flags);
450 hwaddr cpu_get_phys_page_debug(CPUArchState *env, target_ulong addr);
[all …]
Dgdbstub.h17 target_ulong ret, target_ulong err);
/external/qemu/target-i386/
Dshift_helper_template.h22 #define SIGN_MASK (((target_ulong)1) << (DATA_BITS - 1))
55 target_ulong glue(helper_rcl, SUFFIX)(CPUX86State *env, in glue()
56 target_ulong t0, target_ulong t1) in glue()
59 target_ulong src; in glue()
72 res = (t0 << count) | ((target_ulong)(eflags & CC_C) << (count - 1)); in glue()
83 target_ulong glue(helper_rcr, SUFFIX)(CPUX86State *env, in glue()
84 target_ulong t0, target_ulong t1) in glue()
87 target_ulong src; in glue()
100 res = (t0 >> count) | ((target_ulong)(eflags & CC_C) << (DATA_BITS - count)); in glue()
Dint_helper.c44 void helper_divb_AL(CPUX86State *env, target_ulong t0) in helper_divb_AL()
61 void helper_idivb_AL(CPUX86State *env, target_ulong t0) in helper_idivb_AL()
78 void helper_divw_AX(CPUX86State *env, target_ulong t0) in helper_divw_AX()
96 void helper_idivw_AX(CPUX86State *env, target_ulong t0) in helper_idivw_AX()
114 void helper_divl_EAX(CPUX86State *env, target_ulong t0) in helper_divl_EAX()
132 void helper_idivl_EAX(CPUX86State *env, target_ulong t0) in helper_idivl_EAX()
359 void helper_mulq_EAX_T0(CPUX86State *env, target_ulong t0) in helper_mulq_EAX_T0()
370 void helper_imulq_EAX_T0(CPUX86State *env, target_ulong t0) in helper_imulq_EAX_T0()
381 target_ulong helper_imulq_T0_T1(CPUX86State *env, target_ulong t0, target_ulong t1) in helper_imulq_T0_T1()
391 void helper_divq_EAX(CPUX86State *env, target_ulong t0) in helper_divq_EAX()
[all …]
Dcpu.h666 target_ulong base;
738 target_ulong regs[CPU_NB_REGS];
739 target_ulong eip;
740 target_ulong eflags; /* eflags register. During CPU emulation, CC
745 target_ulong cc_src;
746 target_ulong cc_dst;
760 target_ulong cr[5]; /* NOTE: cr1 is unused */
783 target_ulong sysenter_esp;
784 target_ulong sysenter_eip;
800 target_ulong lstar;
[all …]
Dmisc_helper.c73 target_ulong helper_inb(uint32_t port) in helper_inb()
83 target_ulong helper_inw(uint32_t port) in helper_inw()
93 target_ulong helper_inl(uint32_t port) in helper_inl()
130 target_ulong helper_read_crN(CPUX86State *env, int reg) in helper_read_crN()
135 void helper_write_crN(CPUX86State *env, int reg, target_ulong t0) in helper_write_crN()
139 void helper_movl_drN_T0(CPUX86State *env, int reg, target_ulong t0) in helper_movl_drN_T0()
143 target_ulong helper_read_crN(CPUX86State *env, int reg) in helper_read_crN()
145 target_ulong val; in helper_read_crN()
163 void helper_write_crN(CPUX86State *env, int reg, target_ulong t0) in helper_write_crN()
188 void helper_movl_drN_T0(CPUX86State *env, int reg, target_ulong t0) in helper_movl_drN_T0()
[all …]
Dmem_helper.c41 void helper_cmpxchg8b(CPUX86State *env, target_ulong a0) in helper_cmpxchg8b()
62 void helper_cmpxchg16b(CPUX86State *env, target_ulong a0) in helper_cmpxchg16b()
88 void helper_boundw(CPUX86State *env, target_ulong a0, int v) in helper_boundw()
99 void helper_boundl(CPUX86State *env, target_ulong a0, int v) in helper_boundl()
132 void tlb_fill(CPUX86State* env, target_ulong addr, int is_write, int mmu_idx, in tlb_fill()
Dseg_helper.c48 target_ulong ptr; in load_segment()
189 target_ulong tss_base; in switch_tss()
195 target_ulong ptr; in switch_tss()
272 target_ulong ptr; in switch_tss()
324 target_ulong ptr; in switch_tss()
499 target_ulong ptr, ssp; in do_interrupt_protected()
702 static inline target_ulong get_rsp_from_tss(CPUX86State *env, int level) in get_rsp_from_tss()
722 target_ulong next_eip, int is_hw) in do_interrupt64()
725 target_ulong ptr; in do_interrupt64()
729 target_ulong old_eip, esp, offset; in do_interrupt64()
[all …]
/external/qemu/include/sysemu/
Dkvm.h64 int kvm_insert_breakpoint(CPUState *current_env, target_ulong addr,
65 target_ulong len, int type);
66 int kvm_remove_breakpoint(CPUState *current_env, target_ulong addr,
67 target_ulong len, int type);
107 target_ulong pc;
108 target_ulong saved_insn;
118 target_ulong pc);
126 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
127 target_ulong len, int type);
128 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
[all …]
/external/qemu/
Dcputlb.c73 static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr) in tlb_flush_entry()
85 void tlb_flush_page(CPUArchState *env, target_ulong addr) in tlb_flush_page()
128 target_ulong vaddr) in tlb_unprotect_code_phys()
152 static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr) in tlb_set_dirty1()
161 void tlb_set_dirty(CPUArchState *env, target_ulong vaddr) in tlb_set_dirty()
175 static void tlb_add_large_page(CPUArchState *env, target_ulong vaddr, in tlb_add_large_page()
176 target_ulong size) in tlb_add_large_page()
178 target_ulong mask = ~(size - 1); in tlb_add_large_page()
180 if (env->tlb_flush_addr == (target_ulong)-1) { in tlb_add_large_page()
199 void tlb_set_page(CPUArchState *env, target_ulong vaddr, in tlb_set_page()
[all …]
Dtranslate-all.c89 #define V_L1_SIZE ((target_ulong)1 << V_L1_BITS)
656 static TranslationBlock *tb_alloc(target_ulong pc) in tb_alloc()
760 static void tb_invalidate_check(target_ulong address) in tb_invalidate_check()
982 target_ulong pc, target_ulong cs_base, in tb_gen_code()
988 target_ulong virt_page2; in tb_gen_code()
1057 target_ulong current_pc = 0; in tb_invalidate_phys_page_range()
1058 target_ulong current_cs_base = 0; in tb_invalidate_phys_page_range()
1200 target_ulong current_pc = 0; in tb_invalidate_phys_page()
1201 target_ulong current_cs_base = 0; in tb_invalidate_phys_page()
1276 target_ulong addr; in tb_alloc_page()
[all …]
/external/qemu/tcg/
Dtcg.h513 target_ulong gen_opc_pc[OPC_BUF_SIZE];
776 tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr,
778 tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr,
780 tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr,
782 uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr,
784 tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr,
786 tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr,
788 uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr,
792 tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr,
794 tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr,
[all …]
/external/qemu/include/disas/
Ddisas.h11 void target_disas(FILE *out, CPUArchState *env, target_ulong code,
12 target_ulong size, int flags);
15 target_ulong pc, int nb_insn, int is_physical, int flags);
18 const char *lookup_symbol(target_ulong orig_addr);
26 typedef const char *(*lookup_symbol_t)(struct syminfo *s, target_ulong orig_addr);
/external/qemu/include/qemu/
Dlog.h106 void target_disas(FILE*, CPUArchState*, target_ulong, target_ulong, int);
108 static inline void log_target_disas(CPUArchState *env, target_ulong start, in log_target_disas()
109 target_ulong len, int flags) in log_target_disas()
/external/qemu/target-arm/
Darm-semi.c119 static target_ulong arm_semi_syscall_len;
122 static target_ulong syscall_err;
125 static void arm_semi_cb(CPUState *cpu, target_ulong ret, target_ulong err) in arm_semi_cb()
132 if (ret == (target_ulong)-1) { in arm_semi_cb()
156 static void arm_semi_flen_cb(CPUState *cpu, target_ulong ret, target_ulong err) in arm_semi_flen_cb()
183 target_ulong args; in do_arm_semihosting()
184 target_ulong arg0, arg1, arg2, arg3; in do_arm_semihosting()
/external/qemu/include/hw/android/goldfish/
Dvmem.h21 int safe_memory_rw_debug(CPUState *env, target_ulong addr, uint8_t *buf,
24 hwaddr safe_get_phys_page_debug(CPUState *env, target_ulong addr);
/external/qemu/hw/android/goldfish/
Dvmem.c29 int safe_memory_rw_debug(CPUState *cpu, target_ulong addr, uint8_t *buf, in safe_memory_rw_debug()
40 hwaddr safe_get_phys_page_debug(CPUState *cpu, target_ulong addr) in safe_get_phys_page_debug()

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