Searched refs:uncached_cpsr (Results 1 – 5 of 5) sorted by relevance
315 env->uncached_cpsr = ARM_CPU_MODE_USR; in cpu_reset()325 env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I; in cpu_reset()329 env->uncached_cpsr &= ~CPSR_I; in cpu_reset()524 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) | in cpsr_read()555 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) { in cpsr_write()559 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask); in cpsr_write()714 old_mode = env->uncached_cpsr & CPSR_M; in switch_mode()862 env->uncached_cpsr &= ~CPSR_IT; in do_interrupt_v7m()904 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) { in do_interrupt()920 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) { in do_interrupt()[all …]
117 uint32_t uncached_cpsr; member575 if ((env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_USR) { in arm_current_pl()810 return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0; in cpu_mmu_index()818 return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR; in is_cpu_user()892 privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR; in cpu_get_tb_cpu_state()
298 && (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) { in HELPER()313 && (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) { in HELPER()
133 env->uncached_cpsr = val & CPSR_M; in cpu_load()
459 && !(env->uncached_cpsr & CPSR_F)) { in cpu_exec()475 || !(env->uncached_cpsr & CPSR_I))) { in cpu_exec()