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/external/smali/smali-integration-tests/src/test/smali/jumbo-string-tests/
DFormat31c.smali44 const-string/jumbo v0, "99999"
45 invoke-virtual {v0}, Ljava/lang/String;->length()I
52 invoke-virtual {v0, v2}, Ljava/lang/String;->charAt(I)C
70 const-string v0, "99999"
71 invoke-virtual {v0}, Ljava/lang/String;->length()I
78 invoke-virtual {v0, v2}, Ljava/lang/String;->charAt(I)C
95 const-string/jumbo v0, "0"
96 const-string/jumbo v0, "1"
97 const-string/jumbo v0, "2"
98 const-string/jumbo v0, "3"
[all …]
/external/llvm/test/MC/AArch64/
Darm64-advsimd.s5 abs.8b v0, v0
6 abs.16b v0, v0
7 abs.4h v0, v0
8 abs.8h v0, v0
9 abs.2s v0, v0
10 abs.4s v0, v0
12 ; CHECK: abs.8b v0, v0 ; encoding: [0x00,0xb8,0x20,0x0e]
13 ; CHECK: abs.16b v0, v0 ; encoding: [0x00,0xb8,0x20,0x4e]
14 ; CHECK: abs.4h v0, v0 ; encoding: [0x00,0xb8,0x60,0x0e]
15 ; CHECK: abs.8h v0, v0 ; encoding: [0x00,0xb8,0x60,0x4e]
[all …]
Dneon-simd-shift.s8 sshr v0.8b, v1.8b, #3
9 sshr v0.4h, v1.4h, #3
10 sshr v0.2s, v1.2s, #3
11 sshr v0.16b, v1.16b, #3
12 sshr v0.8h, v1.8h, #3
13 sshr v0.4s, v1.4s, #3
14 sshr v0.2d, v1.2d, #3
26 ushr v0.8b, v1.8b, #3
27 ushr v0.4h, v1.4h, #3
28 ushr v0.2s, v1.2s, #3
[all …]
Dneon-3vdiff.s17 saddl v0.8h, v1.8b, v2.8b
18 saddl v0.4s, v1.4h, v2.4h
19 saddl v0.2d, v1.2s, v2.2s
25 saddl2 v0.4s, v1.8h, v2.8h
26 saddl2 v0.8h, v1.16b, v2.16b
27 saddl2 v0.2d, v1.4s, v2.4s
33 uaddl v0.8h, v1.8b, v2.8b
34 uaddl v0.4s, v1.4h, v2.4h
35 uaddl v0.2d, v1.2s, v2.2s
41 uaddl2 v0.8h, v1.16b, v2.16b
[all …]
Dneon-diagnostics.s9 add v0.16b, v1.8b, v2.8b
10 sub v0.2d, v1.2d, v2.2s
24 fadd v0.2d, v1.2s, v2.2s
25 fsub v0.4s, v1.2s, v2.4s
26 fsub v0.8b, v1.8b, v2.8b
43 mul v0.16b, v1.8b, v2.8b
44 mul v0.2d, v1.2d, v2.2d
57 fmul v0.16b, v1.8b, v2.8b
58 fdiv v0.2s, v1.2d, v2.2d
71 and v0.8b, v1.16b, v2.8b
[all …]
Dneon-2velem.s9 mla v0.2s, v1.2s, v2.s[2]
10 mla v0.2s, v1.2s, v22.s[2]
19 mla v0.4h, v1.4h, v2.h[2]
20 mla v0.4h, v1.4h, v15.h[2]
21 mla v0.8h, v1.8h, v2.h[7]
22 mla v0.8h, v1.8h, v14.h[6]
29 mls v0.2s, v1.2s, v2.s[2]
30 mls v0.2s, v1.2s, v22.s[2]
39 mls v0.4h, v1.4h, v2.h[2]
40 mls v0.4h, v1.4h, v15.h[2]
[all …]
Dneon-mov.s9 movi v0.2s, #1
14 movi v0.4s, #1
15 movi v0.4s, #1, lsl #8
16 movi v0.4s, #1, lsl #16
17 movi v0.4s, #1, lsl #24
18 movi v0.4h, #1
19 movi v0.4h, #1, lsl #8
20 movi v0.8h, #1
21 movi v0.8h, #1, lsl #8
40 mvni v0.2s, #1
[all …]
Dneon-simd-ldst-multi-elem.s8 st1 { v0.16b }, [x0]
11 st1 { v0.2d }, [x0]
12 st1 { v0.8b }, [x0]
15 st1 { v0.1d }, [x0]
28 st1 { v0.16b, v1.16b }, [x0]
30 st1 { v31.4s, v0.4s }, [sp]
31 st1 { v0.2d, v1.2d }, [x0]
32 st1 { v0.8b, v1.8b }, [x0]
34 st1 { v31.2s, v0.2s }, [sp]
35 st1 { v0.1d, v1.1d }, [x0]
[all …]
Dneon-perm.s9 uzp1 v0.8b, v1.8b, v2.8b
10 uzp1 v0.16b, v1.16b, v2.16b
11 uzp1 v0.4h, v1.4h, v2.4h
12 uzp1 v0.8h, v1.8h, v2.8h
13 uzp1 v0.2s, v1.2s, v2.2s
14 uzp1 v0.4s, v1.4s, v2.4s
15 uzp1 v0.2d, v1.2d, v2.2d
25 trn1 v0.8b, v1.8b, v2.8b
26 trn1 v0.16b, v1.16b, v2.16b
27 trn1 v0.4h, v1.4h, v2.4h
[all …]
Dneon-simd-ldst-one-elem.s8 ld1r { v0.16b }, [x0]
11 ld1r { v0.2d }, [x0]
12 ld1r { v0.8b }, [x0]
15 ld1r { v0.1d }, [x0]
29 ld2r { v0.16b, v1.16b }, [x0]
31 ld2r { v31.4s, v0.4s }, [sp]
32 ld2r { v0.2d, v1.2d }, [x0]
33 ld2r { v0.8b, v1.8b }, [x0]
35 ld2r { v31.2s, v0.2s }, [sp]
36 ld2r { v31.1d, v0.1d }, [sp]
[all …]
Dneon-simd-post-ldst-multi-elem.s8 ld1 { v0.16b }, [x0], x1
11 ld1 { v0.2d }, [x0], #16
12 ld1 { v0.8b }, [x0], x2
15 ld1 { v0.1d }, [x0], #8
37 ld1 { v0.16b, v1.16b }, [x0], x1
39 ld1 { v31.4s, v0.4s }, [sp], #32
40 ld1 { v0.2d, v1.2d }, [x0], #32
41 ld1 { v0.8b, v1.8b }, [x0], x2
43 ld1 { v31.2s, v0.2s }, [sp], #16
44 ld1 { v0.1d, v1.1d }, [x0], #16
[all …]
Dneon-saturating-add-sub.s9 sqadd v0.8b, v1.8b, v2.8b
10 sqadd v0.16b, v1.16b, v2.16b
11 sqadd v0.4h, v1.4h, v2.4h
12 sqadd v0.8h, v1.8h, v2.8h
13 sqadd v0.2s, v1.2s, v2.2s
14 sqadd v0.4s, v1.4s, v2.4s
15 sqadd v0.2d, v1.2d, v2.2d
28 uqadd v0.8b, v1.8b, v2.8b
29 uqadd v0.16b, v1.16b, v2.16b
30 uqadd v0.4h, v1.4h, v2.4h
[all …]
Dneon-shift.s9 sshl v0.8b, v1.8b, v2.8b
10 sshl v0.16b, v1.16b, v2.16b
11 sshl v0.4h, v1.4h, v2.4h
12 sshl v0.8h, v1.8h, v2.8h
13 sshl v0.2s, v1.2s, v2.2s
14 sshl v0.4s, v1.4s, v2.4s
15 sshl v0.2d, v1.2d, v2.2d
28 ushl v0.8b, v1.8b, v2.8b
29 ushl v0.16b, v1.16b, v2.16b
30 ushl v0.4h, v1.4h, v2.4h
[all …]
Dneon-halving-add-sub.s9 shadd v0.8b, v1.8b, v2.8b
10 shadd v0.16b, v1.16b, v2.16b
11 shadd v0.4h, v1.4h, v2.4h
12 shadd v0.8h, v1.8h, v2.8h
13 shadd v0.2s, v1.2s, v2.2s
14 shadd v0.4s, v1.4s, v2.4s
27 uhadd v0.8b, v1.8b, v2.8b
28 uhadd v0.16b, v1.16b, v2.16b
29 uhadd v0.4h, v1.4h, v2.4h
30 uhadd v0.8h, v1.8h, v2.8h
[all …]
Dneon-aba-abd.s8 uaba v0.8b, v1.8b, v2.8b
9 uaba v0.16b, v1.16b, v2.16b
10 uaba v0.4h, v1.4h, v2.4h
11 uaba v0.8h, v1.8h, v2.8h
12 uaba v0.2s, v1.2s, v2.2s
13 uaba v0.4s, v1.4s, v2.4s
23 saba v0.8b, v1.8b, v2.8b
24 saba v0.16b, v1.16b, v2.16b
25 saba v0.4h, v1.4h, v2.4h
26 saba v0.8h, v1.8h, v2.8h
[all …]
Dneon-add-sub-instructions.s9 add v0.8b, v1.8b, v2.8b
10 add v0.16b, v1.16b, v2.16b
11 add v0.4h, v1.4h, v2.4h
12 add v0.8h, v1.8h, v2.8h
13 add v0.2s, v1.2s, v2.2s
14 add v0.4s, v1.4s, v2.4s
15 add v0.2d, v1.2d, v2.2d
28 sub v0.8b, v1.8b, v2.8b
29 sub v0.16b, v1.16b, v2.16b
30 sub v0.4h, v1.4h, v2.4h
[all …]
Dneon-max-min.s8 smax v0.8b, v1.8b, v2.8b
9 smax v0.16b, v1.16b, v2.16b
10 smax v0.4h, v1.4h, v2.4h
11 smax v0.8h, v1.8h, v2.8h
12 smax v0.2s, v1.2s, v2.2s
13 smax v0.4s, v1.4s, v2.4s
22 umax v0.8b, v1.8b, v2.8b
23 umax v0.16b, v1.16b, v2.16b
24 umax v0.4h, v1.4h, v2.4h
25 umax v0.8h, v1.8h, v2.8h
[all …]
Dneon-max-min-pairwise.s8 smaxp v0.8b, v1.8b, v2.8b
9 smaxp v0.16b, v1.16b, v2.16b
10 smaxp v0.4h, v1.4h, v2.4h
11 smaxp v0.8h, v1.8h, v2.8h
12 smaxp v0.2s, v1.2s, v2.2s
13 smaxp v0.4s, v1.4s, v2.4s
22 umaxp v0.8b, v1.8b, v2.8b
23 umaxp v0.16b, v1.16b, v2.16b
24 umaxp v0.4h, v1.4h, v2.4h
25 umaxp v0.8h, v1.8h, v2.8h
[all …]
Dneon-tbl.s9 tbl v0.8b, { v1.16b }, v2.8b
10 tbl v0.8b, { v1.16b, v2.16b }, v2.8b
11 tbl v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b
12 tbl v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.8b
13 tbl v0.8b, { v31.16b, v0.16b, v1.16b, v2.16b }, v2.8b
21 tbl v0.16b, { v1.16b }, v2.16b
22 tbl v0.16b, { v1.16b, v2.16b }, v2.16b
23 tbl v0.16b, { v1.16b, v2.16b, v3.16b }, v2.16b
24 tbl v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.16b
25 tbl v0.16b, { v30.16b, v31.16b, v0.16b, v1.16b }, v2.16b
[all …]
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-advsimd.txt10 # CHECK: abs.8b v0, v0
11 # CHECK: abs.16b v0, v0
12 # CHECK: abs.4h v0, v0
13 # CHECK: abs.8h v0, v0
14 # CHECK: abs.2s v0, v0
15 # CHECK: abs.4s v0, v0
25 # CHECK: add.8b v0, v0, v0
26 # CHECK: add.16b v0, v0, v0
27 # CHECK: add.4h v0, v0, v0
28 # CHECK: add.8h v0, v0, v0
[all …]
/external/llvm/test/CodeGen/AArch64/
Darm64-subvector-extend.ll9 define <8 x i16> @func1(<8 x i8> %v0) nounwind {
11 ; CHECK-NEXT: ushll.8h v0, v0, #0
13 %r = zext <8 x i8> %v0 to <8 x i16>
17 define <8 x i16> @func2(<8 x i8> %v0) nounwind {
19 ; CHECK-NEXT: sshll.8h v0, v0, #0
21 %r = sext <8 x i8> %v0 to <8 x i16>
25 define <16 x i16> @func3(<16 x i8> %v0) nounwind {
27 ; CHECK-NEXT: ushll2.8h v1, v0, #0
28 ; CHECK-NEXT: ushll.8h v0, v0, #0
30 %r = zext <16 x i8> %v0 to <16 x i16>
[all …]
/external/openssl/crypto/aes/asm/
Daesv8-armx-64.S22 eor v0.16b,v0.16b,v0.16b
34 ext v5.16b,v0.16b,v3.16b,#12
36 aese v6.16b,v0.16b
40 ext v5.16b,v0.16b,v5.16b,#12
42 ext v5.16b,v0.16b,v5.16b,#12
52 ext v5.16b,v0.16b,v3.16b,#12
54 aese v6.16b,v0.16b
57 ext v5.16b,v0.16b,v5.16b,#12
59 ext v5.16b,v0.16b,v5.16b,#12
66 ext v5.16b,v0.16b,v3.16b,#12
[all …]
/external/smali/smali-integration-tests/src/test/smali/junit-tests/InstructionTests/Format3rc/
DRangeMethods.smali14 add-int v0, v1, v2
15 add-int v0, v0, v3
16 add-int v0, v0, v4
17 add-int v0, v0, v5
18 add-int v0, v0, v6
20 return v0
26 add-int v0, v1, v2
27 add-int v0, v0, v3
28 add-int v0, v0, v4
29 add-int v0, v0, v5
[all …]
DRangeMethodsSuper.smali13 add-int v0, v1, v2
14 add-int v0, v0, v3
15 add-int v0, v0, v4
16 add-int v0, v0, v5
17 add-int v0, v0, v6
19 return v0
25 add-int v0, v1, v2
26 add-int v0, v0, v3
27 add-int v0, v0, v4
28 add-int v0, v0, v5
[all …]
/external/valgrind/main/none/tests/mips32/
Dvfp.c331 TESTINSN6LOADw("lwxc1 $f0, $a3($v0)", 0, f0, a3, v0); in main()
332 TESTINSN6LOADw("lwxc1 $f0, $a3($v0)", 4, f0, a3, v0); in main()
333 TESTINSN6LOADw("lwxc1 $f0, $a3($v0)", 8, f0, a3, v0); in main()
334 TESTINSN6LOADw("lwxc1 $f0, $a3($v0)", 12, f0, a3, v0); in main()
335 TESTINSN6LOADw("lwxc1 $f0, $a3($v0)", 16, f0, a3, v0); in main()
336 TESTINSN6LOADw("lwxc1 $f0, $a3($v0)", 20, f0, a3, v0); in main()
337 TESTINSN6LOADw("lwxc1 $f0, $a3($v0)", 24, f0, a3, v0); in main()
338 TESTINSN6LOADw("lwxc1 $f0, $a3($v0)", 28, f0, a3, v0); in main()
339 TESTINSN6LOADw("lwxc1 $f0, $a3($v0)", 32, f0, a3, v0); in main()
340 TESTINSN6LOADw("lwxc1 $f0, $a3($v0)", 36, f0, a3, v0); in main()
[all …]

12345678910>>...33