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Searched refs:v1f64 (Results 1 – 19 of 19) sorted by relevance

/external/llvm/test/CodeGen/AArch64/
Darm64-neon-add-sub.ll164 %2 = tail call <1 x double> @llvm.fma.v1f64(<1 x double> %1, <1 x double> %c, <1 x double> %a)
171 %1 = tail call <1 x double> @llvm.fma.v1f64(<1 x double> %b, <1 x double> %c, <1 x double> %a)
185 %1 = tail call <1 x double> @llvm.aarch64.neon.fabd.v1f64(<1 x double> %a, <1 x double> %b)
192 %1 = tail call <1 x double> @llvm.aarch64.neon.fmax.v1f64(<1 x double> %a, <1 x double> %b)
199 %1 = tail call <1 x double> @llvm.aarch64.neon.fmin.v1f64(<1 x double> %a, <1 x double> %b)
206 %1 = tail call <1 x double> @llvm.aarch64.neon.fmaxnm.v1f64(<1 x double> %a, <1 x double> %b)
213 %1 = tail call <1 x double> @llvm.aarch64.neon.fminnm.v1f64(<1 x double> %a, <1 x double> %b)
220 %1 = tail call <1 x double> @llvm.fabs.v1f64(<1 x double> %a)
231 declare <1 x double> @llvm.fabs.v1f64(<1 x double>)
232 declare <1 x double> @llvm.aarch64.neon.fminnm.v1f64(<1 x double>, <1 x double>)
[all …]
Darm64-extract_subvector.ll45 define <1 x double> @v1f64(<2 x double> %a) nounwind {
46 ; CHECK-LABEL: v1f64:
Darm64-neon-simd-shift.ll635 %1 = tail call <1 x i64> @llvm.aarch64.neon.vcvtfp2fxs.v1i64.v1f64(<1 x double> %a, i32 64)
642 %1 = tail call <1 x i64> @llvm.aarch64.neon.vcvtfp2fxu.v1i64.v1f64(<1 x double> %a, i32 64)
649 %1 = tail call <1 x double> @llvm.aarch64.neon.vcvtfxs2fp.v1f64.v1i64(<1 x i64> %a, i32 64)
656 %1 = tail call <1 x double> @llvm.aarch64.neon.vcvtfxu2fp.v1f64.v1i64(<1 x i64> %a, i32 64)
660 declare <1 x i64> @llvm.aarch64.neon.vcvtfp2fxs.v1i64.v1f64(<1 x double>, i32)
661 declare <1 x i64> @llvm.aarch64.neon.vcvtfp2fxu.v1i64.v1f64(<1 x double>, i32)
662 declare <1 x double> @llvm.aarch64.neon.vcvtfxs2fp.v1f64.v1i64(<1 x i64>, i32)
663 declare <1 x double> @llvm.aarch64.neon.vcvtfxu2fp.v1f64.v1i64(<1 x i64>, i32)
Darm64-indexed-vector-ldst.ll849 %ld2 = tail call { <1 x double>, <1 x double> } @llvm.aarch64.neon.ld2.v1f64.p0f64(double* %A)
858 %ld2 = tail call { <1 x double>, <1 x double> } @llvm.aarch64.neon.ld2.v1f64.p0f64(double* %A)
864 declare { <1 x double>, <1 x double> } @llvm.aarch64.neon.ld2.v1f64.p0f64(double*)
1101 …%ld3 = tail call { <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld3.v1f64.p0f64(d…
1110 …%ld3 = tail call { <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld3.v1f64.p0f64(d…
1116 declare { <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld3.v1f64.p0f64(double*)
1353 … double>, <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld4.v1f64.p0f64(double* %A)
1362 … double>, <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld4.v1f64.p0f64(double* %A)
1368 declare { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld4.v1f64.p0f…
1604 %ld1x2 = tail call { <1 x double>, <1 x double> } @llvm.aarch64.neon.ld1x2.v1f64.p0f64(double* %A)
[all …]
Darm64-ld1.ll296 %tmp2 = call %struct.__neon_float64x1x2_t @llvm.aarch64.neon.ld2.v1f64.p0f64(double* %A)
305 %tmp2 = call %struct.__neon_float64x1x3_t @llvm.aarch64.neon.ld3.v1f64.p0f64(double* %A)
314 %tmp2 = call %struct.__neon_float64x1x4_t @llvm.aarch64.neon.ld4.v1f64.p0f64(double* %A)
318 declare %struct.__neon_float64x1x2_t @llvm.aarch64.neon.ld2.v1f64.p0f64(double*) nounwind readonly
319 declare %struct.__neon_float64x1x3_t @llvm.aarch64.neon.ld3.v1f64.p0f64(double*) nounwind readonly
320 declare %struct.__neon_float64x1x4_t @llvm.aarch64.neon.ld4.v1f64.p0f64(double*) nounwind readonly
1049 declare %struct.__neon_float64x1x2_t @llvm.aarch64.neon.ld1x2.v1f64.p0f64(double*) nounwind readonly
1089 %val = call %struct.__neon_float64x1x2_t @llvm.aarch64.neon.ld1x2.v1f64.p0f64(double* %addr)
1156 declare %struct.__neon_float64x1x3_t @llvm.aarch64.neon.ld1x3.v1f64.p0f64(double*) nounwind readonly
1196 %val = call %struct.__neon_float64x1x3_t @llvm.aarch64.neon.ld1x3.v1f64.p0f64(double* %addr)
[all …]
Darm64-st1.ll388 declare void @llvm.aarch64.neon.st1x2.v1f64.p0f64(<1 x double>, <1 x double>, double*) nounwind rea…
428 call void @llvm.aarch64.neon.st1x2.v1f64.p0f64(<1 x double> %A, <1 x double> %B, double* %addr)
486 declare void @llvm.aarch64.neon.st1x3.v1f64.p0f64(<1 x double>, <1 x double>, <1 x double>, double*…
526 …call void @llvm.aarch64.neon.st1x3.v1f64.p0f64(<1 x double> %A, <1 x double> %B, <1 x double> %C, …
585 declare void @llvm.aarch64.neon.st1x4.v1f64.p0f64(<1 x double>, <1 x double>, <1 x double>, <1 x do…
625 …call void @llvm.aarch64.neon.st1x4.v1f64.p0f64(<1 x double> %A, <1 x double> %B, <1 x double> %C, …
Darm64-neon-simd-ldst-one.ll256 define <1 x double> @testDUP.v1f64(double* %a, double* %b) #0 {
259 ; CHECK-LABEL: testDUP.v1f64:
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h100 v1f64 = 50, // 1 x f64 enumerator
206 SimpleTy == MVT::v1f64 || SimpleTy == MVT::v2f32); in is64BitVector()
305 case v1f64: in getVectorElementType()
356 case v1f64: return 1; in getVectorNumElements()
404 case v1f64: return 64; in getSizeInBits()
561 if (NumElements == 1) return MVT::v1f64; in getVectorVT()
DValueTypes.td74 def v1f64 : ValueType<64, 50>; // 1 x f64 vector value
/external/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp2215 else if (VT == MVT::v1i64 || VT == MVT::v1f64) in Select()
2233 else if (VT == MVT::v1i64 || VT == MVT::v1f64) in Select()
2251 else if (VT == MVT::v1i64 || VT == MVT::v1f64) in Select()
2269 else if (VT == MVT::v1i64 || VT == MVT::v1f64) in Select()
2287 else if (VT == MVT::v1i64 || VT == MVT::v1f64) in Select()
2305 else if (VT == MVT::v1i64 || VT == MVT::v1f64) in Select()
2323 else if (VT == MVT::v1i64 || VT == MVT::v1f64) in Select()
2341 else if (VT == MVT::v1i64 || VT == MVT::v1f64) in Select()
2359 else if (VT == MVT::v1i64 || VT == MVT::v1f64) in Select()
2373 VT == MVT::v1f64) in Select()
[all …]
DAArch64CallingConvention.td61 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32],
70 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8],
95 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32],
136 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32],
146 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8],
162 CCIfType<[i64, f64, v1i64, v2i32, v4i16, v8i8, v1f64, v2f32], CCAssignToStack<8, 8>>,
DAArch64InstrInfo.td1209 defm : VecROLoadPat<ro64, v1f64, LDRDroW, LDRDroX>;
1349 def : Pat<(v1f64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1506 def : Pat<(v1f64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1824 defm : VecROStorePat<ro64, v1f64, FPR64, STRDroW, STRDroX>;
1886 def : Pat<(store (v1f64 FPR64:$Rt),
1977 def : Pat<(store (v1f64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2080 def : Pat<(pre_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2130 def : Pat<(post_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2333 def : Pat<(v1f64 (int_aarch64_neon_frintn (v1f64 FPR64:$Rn))),
2368 def : Pat<(v1f64 (AArch64fmax (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
[all …]
DAArch64ISelLowering.cpp108 addDRTypeForNEON(MVT::v1f64); in AArch64TargetLowering()
389 setOperationAction(ISD::FABS, MVT::v1f64, Expand); in AArch64TargetLowering()
390 setOperationAction(ISD::FADD, MVT::v1f64, Expand); in AArch64TargetLowering()
391 setOperationAction(ISD::FCEIL, MVT::v1f64, Expand); in AArch64TargetLowering()
392 setOperationAction(ISD::FCOPYSIGN, MVT::v1f64, Expand); in AArch64TargetLowering()
393 setOperationAction(ISD::FCOS, MVT::v1f64, Expand); in AArch64TargetLowering()
394 setOperationAction(ISD::FDIV, MVT::v1f64, Expand); in AArch64TargetLowering()
395 setOperationAction(ISD::FFLOOR, MVT::v1f64, Expand); in AArch64TargetLowering()
396 setOperationAction(ISD::FMA, MVT::v1f64, Expand); in AArch64TargetLowering()
397 setOperationAction(ISD::FMUL, MVT::v1f64, Expand); in AArch64TargetLowering()
[all …]
DAArch64RegisterInfo.td392 def FPR64 : RegisterClass<"AArch64", [f64, i64, v2f32, v1f64, v8i8, v4i16, v2i32,
DAArch64InstrFormats.td5323 def : Pat<(v1f64 (OpNode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5336 def : Pat<(v1i64 (OpNode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5482 def : Pat<(v1i64 (OpNode (v1f64 FPR64:$Rn))),
/external/llvm/lib/IR/
DValueTypes.cpp168 case MVT::v1f64: return "v1f64"; in getEVTString()
236 case MVT::v1f64: return VectorType::get(Type::getDoubleTy(Context), 1); in getTypeForEVT()
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp109 case MVT::v1f64: return "MVT::v1f64"; in getEnumName()
/external/llvm/include/llvm/IR/
DIntrinsics.td185 def llvm_v1f64_ty : LLVMType<v1f64>; // 1 x double
/external/llvm/lib/Target/R600/
DSIISelLowering.cpp202 for (int I = MVT::v1f64; I <= MVT::v8f64; ++I) { in SITargetLowering()