Searched refs:v1i16 (Results 1 – 9 of 9) sorted by relevance
| /external/llvm/include/llvm/CodeGen/ |
| D | MachineValueType.h | 72 v1i16 = 26, // 1 x i16 enumerator
192 return (SimpleTy == MVT::v2i8 || SimpleTy == MVT::v1i16 || in is16BitVector()
281 case v1i16: in getVectorElementType()
352 case v1i16: in getVectorNumElements()
385 case v1i16: return 16; in getSizeInBits()
527 if (NumElements == 1) return MVT::v1i16; in getVectorVT()
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| D | ValueTypes.td | 49 def v1i16 : ValueType<16 , 26>; // 1 x i16 vector value
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| /external/llvm/test/CodeGen/AArch64/ |
| D | trunc-v1i64.ll | 6 ; v1i32 trunc v1i64, v1i16 trunc v1i64, v1i8 trunc v1i64.
12 ; Just like v1i16 and v1i8, there is no XTN generated.
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| D | arm64-neon-copy.ll | 858 define <8 x i16> @testDUP.v1i16(<1 x i16> %a) {
859 ; CHECK-LABEL: testDUP.v1i16:
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| /external/llvm/lib/IR/ |
| D | ValueTypes.cpp | 144 case MVT::v1i16: return "v1i16"; in getEVTString()
212 case MVT::v1i16: return VectorType::get(Type::getInt16Ty(Context), 1); in getTypeForEVT()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenTarget.cpp | 85 case MVT::v1i16: return "MVT::v1i16"; in getEnumName()
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| /external/llvm/include/llvm/IR/ |
| D | Intrinsics.td | 159 def llvm_v1i16_ty : LLVMType<v1i16>; // 1 x i16
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrFormats.td | 5298 def v1i16 : BaseSIMDThreeScalar<U, 0b01, opc, FPR16, asm, []>;
5311 def v1i16 : BaseSIMDThreeScalar<U, 0b01, opc, FPR16, asm, []>;
5515 def v1i16 : BaseSIMDTwoScalar<U, 0b01, opc, FPR16, FPR16, asm, []>;
5530 def v1i16 : BaseSIMDTwoScalarTied<U, 0b01, opc, FPR16, FPR16, asm, []>;
5545 def v1i16 : BaseSIMDTwoScalar<U, 0b01, opc, FPR16, FPR32, asm, []>;
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| D | AArch64ISelLowering.cpp | 7924 if (SVT == MVT::v1i8 || SVT == MVT::v1i16 || SVT == MVT::v1i32 in getPreferredVectorAction()
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