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/external/llvm/test/Analysis/CostModel/X86/
Dscalarize.ll14 declare %i8 @llvm.bswap.v2i64(%i8)
17 declare %i8 @llvm.ctpop.v2i64(%i8)
27 ; CHECK32: cost of 10 {{.*}}bswap.v2i64
28 ; CHECK64: cost of 6 {{.*}}bswap.v2i64
29 %r3 = call %i8 @llvm.bswap.v2i64(%i8 undef)
34 ; CHECK32: cost of 10 {{.*}}ctpop.v2i64
35 ; CHECK64: cost of 6 {{.*}}ctpop.v2i64
36 %r5 = call %i8 @llvm.ctpop.v2i64(%i8 undef)
/external/llvm/test/CodeGen/X86/
Dvec_ctbits.ll3 declare <2 x i64> @llvm.cttz.v2i64(<2 x i64>, i1)
4 declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>, i1)
5 declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>)
8 %c = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %a, i1 true)
16 %c = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %a, i1 true)
27 %c = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %a)
/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp214 { ISD::SHL, MVT::v2i64, 1 }, in getArithmeticInstrCost()
215 { ISD::SRL, MVT::v2i64, 1 }, in getArithmeticInstrCost()
262 { ISD::SHL, MVT::v2i64, 1 }, // psllq. in getArithmeticInstrCost()
267 { ISD::SRL, MVT::v2i64, 1 }, // psrlq. in getArithmeticInstrCost()
317 { ISD::SHL, MVT::v2i64, 2*10 }, // Scalarized. in getArithmeticInstrCost()
323 { ISD::SRL, MVT::v2i64, 2*10 }, // Scalarized. in getArithmeticInstrCost()
328 { ISD::SRA, MVT::v2i64, 2*10 }, // Scalarized. in getArithmeticInstrCost()
339 { ISD::SDIV, MVT::v2i64, 2*20 }, in getArithmeticInstrCost()
343 { ISD::UDIV, MVT::v2i64, 2*20 }, in getArithmeticInstrCost()
389 { ISD::MUL, MVT::v2i64, 9 }, in getArithmeticInstrCost()
[all …]
DX86InstrSSE.td336 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
337 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
349 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)),
377 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
378 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
379 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
380 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
381 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
382 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
387 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
[all …]
/external/llvm/test/CodeGen/AArch64/
Darm64-vcvt_n.ll35 %vcvt_n1 = tail call <2 x double> @llvm.aarch64.neon.vcvtfxu2fp.v2f64.v2i64(<2 x i64> %a, i32 12)
40 %vcvt_n1 = tail call <2 x double> @llvm.aarch64.neon.vcvtfxs2fp.v2f64.v2i64(<2 x i64> %a, i32 9)
48 declare <2 x double> @llvm.aarch64.neon.vcvtfxu2fp.v2f64.v2i64(<2 x i64>, i32) nounwind readnone
49 declare <2 x double> @llvm.aarch64.neon.vcvtfxs2fp.v2f64.v2i64(<2 x i64>, i32) nounwind readnone
Darm64-vcvt.ll26 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtas.v2i64.v2f64(<2 x double> %A)
32 declare <2 x i64> @llvm.aarch64.neon.fcvtas.v2i64.v2f64(<2 x double>) nounwind readnone
57 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtau.v2i64.v2f64(<2 x double> %A)
63 declare <2 x i64> @llvm.aarch64.neon.fcvtau.v2i64.v2f64(<2 x double>) nounwind readnone
88 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtms.v2i64.v2f64(<2 x double> %A)
94 declare <2 x i64> @llvm.aarch64.neon.fcvtms.v2i64.v2f64(<2 x double>) nounwind readnone
119 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtmu.v2i64.v2f64(<2 x double> %A)
125 declare <2 x i64> @llvm.aarch64.neon.fcvtmu.v2i64.v2f64(<2 x double>) nounwind readnone
150 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtps.v2i64.v2f64(<2 x double> %A)
156 declare <2 x i64> @llvm.aarch64.neon.fcvtps.v2i64.v2f64(<2 x double>) nounwind readnone
[all …]
Darm64-neon-2velem-high.ll7 declare <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32>, <2 x i32>)
9 declare <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64>, <2 x i64>)
15 declare <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64>, <2 x i64>)
19 declare <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32>, <2 x i32>)
23 declare <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32>, <2 x i32>)
49 …%vmull9.i.i = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32>…
75 …%vmull9.i.i = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32>…
101 …%vqdmull9.i.i = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %shuffle.i.i, <2 x …
128 …%vmull2.i.i.i = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %shuffle.i.i, <2 x i3…
156 …%vmull2.i.i.i = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %shuffle.i.i, <2 x i3…
[all …]
Darm64-neon-2velem.ll25 declare <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32>, <2 x i32>)
29 declare <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64>, <2 x i64>)
33 declare <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64>, <2 x i64>)
37 declare <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32>, <2 x i32>)
41 declare <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32>, <2 x i32>)
577 %vmull2.i = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %b, <2 x i32> %shuffle)
599 %vmull2.i = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %b, <2 x i32> %shuffle)
623 …%vmull2.i = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %shuffle.i, <2 x i32> %sh…
647 …%vmull2.i = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %shuffle.i, <2 x i32> %sh…
669 %vmull2.i = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %b, <2 x i32> %shuffle)
[all …]
Darm64-vmul.ll27 %tmp3 = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
33 declare <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
58 %tmp3 = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
64 declare <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
80 %tmp3 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
102 %tmp3 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
108 declare <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
271 %tmp4 = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
293 %tmp4 = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
299 declare <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64>, <2 x i64>)
[all …]
Dneon-truncStore-extLoad.ll5 define void @truncStore.v2i64(<2 x i64> %a, <2 x i32>* %result) {
6 ; CHECK-LABEL: truncStore.v2i64:
/external/llvm/lib/Target/AArch64/
DAArch64CallingConvention.td27 CCIfType<[v2f64, v4f32], CCBitConvertToType<v2i64>>,
33 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v16i8],
64 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64],
72 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64],
78 CCIfType<[v2f64, v4f32], CCBitConvertToType<v2i64>>,
84 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v16i8],
98 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64],
109 CCIfType<[v2f64, v4f32, f128], CCBitConvertToType<v2i64>>,
139 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64],
148 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64], CCAssignToStack<16, 16>>
[all …]
DAArch64TargetTransformInfo.cpp310 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, in getCastInstrCost()
313 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, in getCastInstrCost()
318 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 }, in getCastInstrCost()
321 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 }, in getCastInstrCost()
341 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, in getCastInstrCost()
344 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, in getCastInstrCost()
347 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 2 }, in getCastInstrCost()
350 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 2 }, in getCastInstrCost()
DAArch64ISelDAGToDAG.cpp497 case MVT::v2i64: in SelectMULLV64LaneV128()
508 case MVT::v2i64: in SelectMULLV64LaneV128()
2217 else if (VT == MVT::v2i64 || VT == MVT::v2f64) in Select()
2235 else if (VT == MVT::v2i64 || VT == MVT::v2f64) in Select()
2253 else if (VT == MVT::v2i64 || VT == MVT::v2f64) in Select()
2271 else if (VT == MVT::v2i64 || VT == MVT::v2f64) in Select()
2289 else if (VT == MVT::v2i64 || VT == MVT::v2f64) in Select()
2307 else if (VT == MVT::v2i64 || VT == MVT::v2f64) in Select()
2325 else if (VT == MVT::v2i64 || VT == MVT::v2f64) in Select()
2343 else if (VT == MVT::v2i64 || VT == MVT::v2f64) in Select()
[all …]
/external/llvm/lib/Target/ARM/
DARMCallingConv.td28 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
47 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
61 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
80 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
96 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
147 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
157 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
175 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
190 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
DARMTargetTransformInfo.cpp217 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1 }, in getCastInstrCost()
218 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i32, 1 }, in getCastInstrCost()
456 {ISD::VECTOR_SHUFFLE, MVT::v2i64, 1}, in getShuffleCost()
478 {ISD::VECTOR_SHUFFLE, MVT::v2i64, 1}, in getShuffleCost()
531 { ISD::SDIV, MVT::v2i64, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
532 { ISD::UDIV, MVT::v2i64, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
533 { ISD::SREM, MVT::v2i64, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
534 { ISD::UREM, MVT::v2i64, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
568 if (LT.second == MVT::v2i64 && in getArithmeticInstrCost()
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h84 v2i64 = 38, // 2 x i64 enumerator
212 SimpleTy == MVT::v4i32 || SimpleTy == MVT::v2i64 || in is128BitVector()
293 case v2i64: in getVectorElementType()
347 case v2i64: in getVectorNumElements()
412 case v2i64: in getSizeInBits()
543 if (NumElements == 2) return MVT::v2i64; in getVectorVT()
/external/llvm/test/CodeGen/ARM/
Dvqdmul.ll175 %tmp3 = call <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
193 …%1 = tail call <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32> %arg0_int32x2_t, <2 x i32> %0) ; <…
198 declare <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
217 %tmp4 = call <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32> %tmp2, <2 x i32> %tmp3)
218 %tmp5 = call <2 x i64> @llvm.arm.neon.vqadds.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp4)
237 %1 = tail call <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32> %arg1_int32x2_t, <2 x i32> %0)
238 %2 = call <2 x i64> @llvm.arm.neon.vqadds.v2i64(<2 x i64> %arg0_int64x2_t, <2 x i64> %1)
243 declare <2 x i64> @llvm.arm.neon.vqadds.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
262 %tmp4 = call <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32> %tmp2, <2 x i32> %tmp3)
263 %tmp5 = call <2 x i64> @llvm.arm.neon.vqsubs.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp4)
[all …]
D2010-06-29-PartialRedefFastAlloc.ll19 %0 = call <2 x i64> @llvm.arm.neon.vld1.v2i64(i8* %arg, i32 1)
25 declare <2 x i64> @llvm.arm.neon.vld1.v2i64(i8*, i32) nounwind readonly
Dvpadal.ll80 %tmp3 = call <2 x i64> @llvm.arm.neon.vpadals.v2i64.v4i32(<2 x i64> %tmp1, <4 x i32> %tmp2)
107 %tmp3 = call <2 x i64> @llvm.arm.neon.vpadalu.v2i64.v4i32(<2 x i64> %tmp1, <4 x i32> %tmp2)
121 declare <2 x i64> @llvm.arm.neon.vpadals.v2i64.v4i32(<2 x i64>, <4 x i32>) nounwind readnone
125 declare <2 x i64> @llvm.arm.neon.vpadalu.v2i64.v4i32(<2 x i64>, <4 x i32>) nounwind readnone
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
DAMDILISelLowering.cpp66 (int)MVT::v2i64 in InitAMDILLowering()
94 (int)MVT::v2i64 in InitAMDILLowering()
122 if (VT != MVT::i64 && VT != MVT::v2i64) { in InitAMDILLowering()
175 setOperationAction(ISD::MULHU, MVT::v2i64, Expand); in InitAMDILLowering()
177 setOperationAction(ISD::MULHS, MVT::v2i64, Expand); in InitAMDILLowering()
178 setOperationAction(ISD::ADD, MVT::v2i64, Expand); in InitAMDILLowering()
179 setOperationAction(ISD::SREM, MVT::v2i64, Expand); in InitAMDILLowering()
181 setOperationAction(ISD::SDIV, MVT::v2i64, Expand); in InitAMDILLowering()
182 setOperationAction(ISD::TRUNCATE, MVT::v2i64, Expand); in InitAMDILLowering()
183 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Expand); in InitAMDILLowering()
[all …]
/external/mesa3d/src/gallium/drivers/radeon/
DAMDILISelLowering.cpp66 (int)MVT::v2i64 in InitAMDILLowering()
94 (int)MVT::v2i64 in InitAMDILLowering()
122 if (VT != MVT::i64 && VT != MVT::v2i64) { in InitAMDILLowering()
175 setOperationAction(ISD::MULHU, MVT::v2i64, Expand); in InitAMDILLowering()
177 setOperationAction(ISD::MULHS, MVT::v2i64, Expand); in InitAMDILLowering()
178 setOperationAction(ISD::ADD, MVT::v2i64, Expand); in InitAMDILLowering()
179 setOperationAction(ISD::SREM, MVT::v2i64, Expand); in InitAMDILLowering()
181 setOperationAction(ISD::SDIV, MVT::v2i64, Expand); in InitAMDILLowering()
182 setOperationAction(ISD::TRUNCATE, MVT::v2i64, Expand); in InitAMDILLowering()
183 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Expand); in InitAMDILLowering()
[all …]
/external/llvm/test/CodeGen/Mips/msa/
Dbasic_operations.ll8 @v2i64 = global <2 x i64> <i64 0, i64 0>
113 store volatile <2 x i64> <i64 0, i64 0>, <2 x i64>*@v2i64
116 store volatile <2 x i64> <i64 72340172838076673, i64 72340172838076673>, <2 x i64>*@v2i64
119 store volatile <2 x i64> <i64 281479271743489, i64 281479271743489>, <2 x i64>*@v2i64
122 store volatile <2 x i64> <i64 4294967297, i64 4294967297>, <2 x i64>*@v2i64
125 store volatile <2 x i64> <i64 1, i64 1>, <2 x i64>*@v2i64
128 store volatile <2 x i64> <i64 1, i64 31>, <2 x i64>*@v2i64
132 store volatile <2 x i64> <i64 3, i64 4>, <2 x i64>*@v2i64
252 store volatile <2 x i64> %2, <2 x i64>*@v2i64
315 %1 = load <2 x i64>* @v2i64
[all …]
Dendian.ll7 @v2i64 = global <2 x i64> <i64 0, i64 0>
104 store volatile <2 x i64> <i64 1, i64 2>, <2 x i64>*@v2i64
/external/llvm/lib/Target/PowerPC/
DPPCInstrVSX.td522 [(set v2i64:$XT, (fp_to_sint v2f64:$XB))]>;
529 [(set v2i64:$XT, (fp_to_uint v2f64:$XB))]>;
552 [(set v2f64:$XT, (sint_to_fp v2i64:$XB))]>;
565 [(set v2f64:$XT, (uint_to_fp v2i64:$XB))]>;
779 def : Pat<(v2i64 (bitconvert v4f32:$A)),
781 def : Pat<(v2i64 (bitconvert v4i32:$A)),
783 def : Pat<(v2i64 (bitconvert v8i16:$A)),
785 def : Pat<(v2i64 (bitconvert v16i8:$A)),
788 def : Pat<(v4f32 (bitconvert v2i64:$A)),
790 def : Pat<(v4i32 (bitconvert v2i64:$A)),
[all …]
/external/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td153 (v2i64 (vector_insert node:$vec, node:$val, node:$idx))>;
162 (v2i64 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
170 def vfsetoeq_v2f64 : vfsetcc_type<v2i64, v2f64, SETOEQ>;
172 def vfsetoge_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGE>;
174 def vfsetogt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGT>;
176 def vfsetole_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLE>;
178 def vfsetolt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLT>;
180 def vfsetone_v2f64 : vfsetcc_type<v2i64, v2f64, SETONE>;
182 def vfsetord_v2f64 : vfsetcc_type<v2i64, v2f64, SETO>;
184 def vfsetun_v2f64 : vfsetcc_type<v2i64, v2f64, SETUO>;
[all …]

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