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/external/llvm/test/CodeGen/X86/
Dvector-intrinsics.ll3 declare <4 x double> @llvm.sin.v4f64(<4 x double> %p)
4 declare <4 x double> @llvm.cos.v4f64(<4 x double> %p)
5 declare <4 x double> @llvm.pow.v4f64(<4 x double> %p, <4 x double> %q)
6 declare <4 x double> @llvm.powi.v4f64(<4 x double> %p, i32)
10 %t = call <4 x double> @llvm.sin.v4f64(<4 x double> %p)
15 %t = call <4 x double> @llvm.cos.v4f64(<4 x double> %p)
20 %t = call <4 x double> @llvm.pow.v4f64(<4 x double> %p, <4 x double> %q)
25 %t = call <4 x double> @llvm.powi.v4f64(<4 x double> %p, i32 %q)
Dvec_floor.ll26 %t = call <4 x double> @llvm.floor.v4f64(<4 x double> %p)
29 declare <4 x double> @llvm.floor.v4f64(<4 x double> %p)
62 %t = call <4 x double> @llvm.ceil.v4f64(<4 x double> %p)
65 declare <4 x double> @llvm.ceil.v4f64(<4 x double> %p)
98 %t = call <4 x double> @llvm.trunc.v4f64(<4 x double> %p)
101 declare <4 x double> @llvm.trunc.v4f64(<4 x double> %p)
134 %t = call <4 x double> @llvm.rint.v4f64(<4 x double> %p)
137 declare <4 x double> @llvm.rint.v4f64(<4 x double> %p)
170 %t = call <4 x double> @llvm.nearbyint.v4f64(<4 x double> %p)
173 declare <4 x double> @llvm.nearbyint.v4f64(<4 x double> %p)
Dvec_fabs.ll26 %t = call <4 x double> @llvm.fabs.v4f64(<4 x double> %p)
29 declare <4 x double> @llvm.fabs.v4f64(<4 x double> %p)
Dfma.ll68 …%add = tail call <4 x double> @llvm.fma.v4f64(<4 x double> %x, <4 x double> %y, <4 x double> %acc.…
80 declare <4 x double> @llvm.fma.v4f64(<4 x double>, <4 x double>, <4 x double>) nounwind readnone
/external/llvm/test/CodeGen/PowerPC/
Dvec_rounding.ll19 declare <4 x double> @llvm.floor.v4f64(<4 x double> %p)
22 %t = call <4 x double> @llvm.floor.v4f64(<4 x double> %p)
41 declare <4 x double> @llvm.ceil.v4f64(<4 x double> %p)
44 %t = call <4 x double> @llvm.ceil.v4f64(<4 x double> %p)
63 declare <4 x double> @llvm.trunc.v4f64(<4 x double> %p)
66 %t = call <4 x double> @llvm.trunc.v4f64(<4 x double> %p)
85 declare <4 x double> @llvm.nearbyint.v4f64(<4 x double> %p)
88 %t = call <4 x double> @llvm.nearbyint.v4f64(<4 x double> %p)
Dvec_fmuladd.ll10 declare <4 x double> @llvm.fmuladd.v4f64(<4 x double> %val, <4 x double>, <4 x double>)
49 …%fmuladd = call <4 x double> @llvm.fmuladd.v4f64 (<4 x double> %x, <4 x double> %x, <4 x double> %…
Dvec_sqrt.ll13 declare <4 x double> @llvm.sqrt.v4f64(<4 x double> %val)
64 %sqrt = call <4 x double> @llvm.sqrt.v4f64 (<4 x double> %x)
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h102 v4f64 = 52, // 4 x f64 enumerator
218 return (SimpleTy == MVT::v8f32 || SimpleTy == MVT::v4f64 || in is256BitVector()
307 case v4f64: in getVectorElementType()
342 case v4f64: return 4; in getVectorNumElements()
421 case v4f64: return 256; in getSizeInBits()
563 if (NumElements == 4) return MVT::v4f64; in getVectorVT()
DValueTypes.td76 def v4f64 : ValueType<256, 52>; // 4 x f64 vector value
/external/llvm/lib/Target/X86/
DX86InstrFMA.td103 loadv4f64, X86Fmadd, v2f64, v4f64>, VEX_W;
105 loadv4f64, X86Fmsub, v2f64, v4f64>, VEX_W;
108 v2f64, v4f64>, VEX_W;
111 v2f64, v4f64>, VEX_W;
123 loadv4f64, X86Fnmadd, v2f64, v4f64>, VEX_W;
126 v4f64>, VEX_W;
377 defm VFMADDPD4 : fma4p<0x69, "vfmaddpd", X86Fmadd, v2f64, v4f64,
379 defm VFMSUBPD4 : fma4p<0x6D, "vfmsubpd", X86Fmsub, v2f64, v4f64,
381 defm VFNMADDPD4 : fma4p<0x79, "vfnmaddpd", X86Fnmadd, v2f64, v4f64,
383 defm VFNMSUBPD4 : fma4p<0x7D, "vfnmsubpd", X86Fnmsub, v2f64, v4f64,
[all …]
DX86TargetTransformInfo.cpp435 {ISD::VECTOR_SHUFFLE, MVT::v4f64, 1}, // vblendpd in getShuffleCost()
629 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, in getCastInstrCost()
630 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 }, in getCastInstrCost()
631 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 }, in getCastInstrCost()
632 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, in getCastInstrCost()
642 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, in getCastInstrCost()
643 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, in getCastInstrCost()
644 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, in getCastInstrCost()
645 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 }, in getCastInstrCost()
652 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 4*10 }, in getCastInstrCost()
[all …]
DX86CallingConv.td49 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
105 CCIfType<[v8f32, v4f64, v8i32, v4i64],
249 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
271 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
295 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>,
419 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
427 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
557 CCIfType<[v8f32, v4f64, v8i32, v4i64],
DX86InstrSSE.td338 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (iPTR 0))),
339 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
352 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
371 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
412 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
413 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
414 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
415 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
416 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
419 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
[all …]
DX86InstrFragmentsSIMD.td308 def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>;
319 def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>;
379 (v4f64 (alignedload256 node:$ptr))>;
426 def memopv4f64 : PatFrag<(ops node:$ptr), (v4f64 (memop node:$ptr))>;
DX86InstrAVX512.td51 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
53 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
58 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
63 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
[all …]
/external/llvm/test/CodeGen/R600/
Dllvm.rint.f64.ll37 %0 = call <4 x double> @llvm.rint.v4f64(<4 x double> %in)
45 declare <4 x double> @llvm.rint.v4f64(<4 x double>) #0
Dfcopysign.f64.ll5 declare <4 x double> @llvm.copysign.v4f64(<4 x double>, <4 x double>) nounwind readnone
34 %result = call <4 x double> @llvm.copysign.v4f64(<4 x double> %mag, <4 x double> %sign)
Dfnearbyint.ll12 declare <4 x double> @llvm.nearbyint.v4f64(<4 x double>) #0
51 %0 = call <4 x double> @llvm.nearbyint.v4f64(<4 x double> %in)
Dfceil64.ll7 declare <4 x double> @llvm.ceil.v4f64(<4 x double>) nounwind readnone
62 %y = call <4 x double> @llvm.ceil.v4f64(<4 x double> %x) nounwind readnone
Dffloor.ll7 declare <4 x double> @llvm.floor.v4f64(<4 x double>) nounwind readnone
63 %y = call <4 x double> @llvm.floor.v4f64(<4 x double> %x) nounwind readnone
Dfma.ll9 declare <4 x double> @llvm.fma.v4f64(<4 x double>, <4 x double>, <4 x double>) nounwind readnone
86 … %r3 = tail call <4 x double> @llvm.fma.v4f64(<4 x double> %r0, <4 x double> %r1, <4 x double> %r2)
/external/llvm/test/Transforms/LoopVectorize/
Dintrinsic.ll33 ;CHECK: llvm.sqrt.v4f64
85 ;CHECK: llvm.sin.v4f64
137 ;CHECK: llvm.cos.v4f64
189 ;CHECK: llvm.exp.v4f64
241 ;CHECK: llvm.exp2.v4f64
293 ;CHECK: llvm.log.v4f64
345 ;CHECK: llvm.log10.v4f64
397 ;CHECK: llvm.log2.v4f64
551 ;CHECK: llvm.floor.v4f64
603 ;CHECK: llvm.ceil.v4f64
[all …]
/external/llvm/test/CodeGen/AArch64/
Darm64-fmuladd.ll78 …%tmp4 = call <4 x double> @llvm.fmuladd.v4f64(<4 x double> %tmp1, <4 x double> %tmp2, <4 x double>…
88 declare <4 x double> @llvm.fmuladd.v4f64(<4 x double>, <4 x double>, <4 x double>) nounwind readnone
/external/llvm/lib/Target/X86/InstPrinter/
DX86InstComments.cpp321 DecodeSHUFPMask(MVT::v4f64, in EmitAnyX86InstComments()
367 DecodeUNPCKLMask(MVT::v4f64, ShuffleMask); in EmitAnyX86InstComments()
403 DecodeUNPCKHMask(MVT::v4f64, ShuffleMask); in EmitAnyX86InstComments()
460 DecodePSHUFMask(MVT::v4f64, in EmitAnyX86InstComments()
/external/llvm/lib/IR/
DValueTypes.cpp170 case MVT::v4f64: return "v4f64"; in getEVTString()
238 case MVT::v4f64: return VectorType::get(Type::getDoubleTy(Context), 4); in getTypeForEVT()

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