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Searched refs:v8f64 (Results 1 – 15 of 15) sorted by relevance

/external/llvm/include/llvm/CodeGen/
DMachineValueType.h103 v8f64 = 53, // 8 x f64 enumerator
106 LAST_FP_VECTOR_VALUETYPE = v8f64,
109 LAST_VECTOR_VALUETYPE = v8f64,
225 return (SimpleTy == MVT::v8f64 || SimpleTy == MVT::v16f32 || in is512BitVector()
308 case v8f64: return f64; in getVectorElementType()
334 case v8f64: return 8; in getVectorNumElements()
427 case v8f64: return 512; in getSizeInBits()
564 if (NumElements == 8) return MVT::v8f64; in getVectorVT()
DValueTypes.td77 def v8f64 : ValueType<512, 53>; // 8 x f64 vector value
/external/llvm/lib/Target/X86/
DX86InstrAVX512.td4 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
12 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
15 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
16 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
96 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
157 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
174 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
[all …]
DX86InstrFragmentsSIMD.td313 def loadv8f64 : PatFrag<(ops node:$ptr), (v8f64 (load node:$ptr))>;
320 def extloadv8f32 : PatFrag<(ops node:$ptr), (v8f64 (extloadvf32 node:$ptr))>;
389 (v8f64 (alignedload512 node:$ptr))>;
431 def memopv8f64 : PatFrag<(ops node:$ptr), (v8f64 (memop8 node:$ptr))>;
488 def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>;
DX86CallingConv.td55 CCIfType<[v16i32, v8i64, v16f32, v8f64],
109 CCIfType<[v16f32, v8f64, v16i32, v8i64],
255 CCIfNotVarArg<CCIfType<[v16i32, v8i64, v16f32, v8f64],
275 CCIfType<[v16i32, v8i64, v16f32, v8f64],
298 CCIfType<[v16i32, v16f32, v8f64, v8i64], CCPassIndirect<i64>>,
561 CCIfType<[v16f32, v8f64, v16i32, v8i64],
DX86RegisterInfo.td452 def VR512 : RegisterClass<"X86", [v16f32, v8f64, v16i32, v8i64], 512,
DX86ISelLowering.cpp1332 addRegisterClass(MVT::v8f64, &X86::VR512RegClass); in resetOperationActions()
1345 setOperationAction(ISD::LOAD, MVT::v8f64, Legal); in resetOperationActions()
1357 setOperationAction(ISD::FADD, MVT::v8f64, Legal); in resetOperationActions()
1358 setOperationAction(ISD::FSUB, MVT::v8f64, Legal); in resetOperationActions()
1359 setOperationAction(ISD::FMUL, MVT::v8f64, Legal); in resetOperationActions()
1360 setOperationAction(ISD::FDIV, MVT::v8f64, Legal); in resetOperationActions()
1361 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal); in resetOperationActions()
1362 setOperationAction(ISD::FNEG, MVT::v8f64, Custom); in resetOperationActions()
1363 setOperationAction(ISD::FMA, MVT::v8f64, Legal); in resetOperationActions()
1401 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom); in resetOperationActions()
[all …]
DX86InstrCompiler.td840 (v8f64 (X86cmov VR512:$t, VR512:$f, imm:$cond,
/external/llvm/test/CodeGen/R600/
Dfceil64.ll8 declare <8 x double> @llvm.ceil.v8f64(<8 x double>) nounwind readnone
77 %y = call <8 x double> @llvm.ceil.v8f64(<8 x double> %x) nounwind readnone
Dffloor.ll8 declare <8 x double> @llvm.floor.v8f64(<8 x double>) nounwind readnone
78 %y = call <8 x double> @llvm.floor.v8f64(<8 x double> %x) nounwind readnone
/external/llvm/lib/IR/
DValueTypes.cpp171 case MVT::v8f64: return "v8f64"; in getEVTString()
239 case MVT::v8f64: return VectorType::get(Type::getDoubleTy(Context), 8); in getTypeForEVT()
/external/llvm/test/CodeGen/X86/
Davx512-arith.ll352 declare <8 x double> @llvm.sqrt.v8f64(<8 x double>)
354 %b = call <8 x double> @llvm.sqrt.v8f64(<8 x double> %a)
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp112 case MVT::v8f64: return "MVT::v8f64"; in getEnumName()
/external/llvm/include/llvm/IR/
DIntrinsics.td188 def llvm_v8f64_ty : LLVMType<v8f64>; // 8 x double
/external/llvm/lib/Target/R600/
DSIISelLowering.cpp202 for (int I = MVT::v1f64; I <= MVT::v8f64; ++I) { in SITargetLowering()