Home
last modified time | relevance | path

Searched refs:v8i32 (Results 1 – 25 of 28) sorted by relevance

12

/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp194 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence in getArithmeticInstrCost()
195 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence in getArithmeticInstrCost()
211 { ISD::SHL, MVT::v8i32, 1 }, in getArithmeticInstrCost()
212 { ISD::SRL, MVT::v8i32, 1 }, in getArithmeticInstrCost()
213 { ISD::SRA, MVT::v8i32, 1 }, in getArithmeticInstrCost()
232 { ISD::SDIV, MVT::v8i32, 8*20 }, in getArithmeticInstrCost()
236 { ISD::UDIV, MVT::v8i32, 8*20 }, in getArithmeticInstrCost()
357 { ISD::MUL, MVT::v8i32, 4 }, in getArithmeticInstrCost()
358 { ISD::SUB, MVT::v8i32, 4 }, in getArithmeticInstrCost()
359 { ISD::ADD, MVT::v8i32, 4 }, in getArithmeticInstrCost()
[all …]
DX86InstrAVX512.td52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
62 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
74 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
[all …]
DX86InstrSSE.td331 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
332 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
354 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
413 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
417 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
423 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
430 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
432 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
433 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
434 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
[all …]
DX86CallingConv.td49 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
105 CCIfType<[v8f32, v4f64, v8i32, v4i64],
249 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
271 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
295 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>,
419 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
427 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
557 CCIfType<[v8f32, v4f64, v8i32, v4i64],
DX86ISelLowering.cpp1139 addRegisterClass(MVT::v8i32, &X86::VR256RegClass); in resetOperationActions()
1178 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal); in resetOperationActions()
1181 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal); in resetOperationActions()
1200 setOperationAction(ISD::SETCC, MVT::v8i32, Custom); in resetOperationActions()
1209 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom); in resetOperationActions()
1213 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom); in resetOperationActions()
1216 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom); in resetOperationActions()
1219 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom); in resetOperationActions()
1236 setOperationAction(ISD::ADD, MVT::v8i32, Legal); in resetOperationActions()
1241 setOperationAction(ISD::SUB, MVT::v8i32, Legal); in resetOperationActions()
[all …]
DX86RegisterInfo.td438 def VR256 : RegisterClass<"X86", [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
463 def VR256X : RegisterClass<"X86", [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
/external/llvm/test/CodeGen/R600/
Dllvm.SI.gather4.ll85 …%r = call <4 x float> @llvm.SI.gather4.b.cl.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> unde…
152 …%r = call <4 x float> @llvm.SI.gather4.cl.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> unde…
178 …%r = call <4 x float> @llvm.SI.gather4.l.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef…
204 …%r = call <4 x float> @llvm.SI.gather4.b.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef…
217 …%r = call <4 x float> @llvm.SI.gather4.b.cl.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> un…
271 …%r = call <4 x float> @llvm.SI.gather4.c.cl.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> unde…
297 …%r = call <4 x float> @llvm.SI.gather4.c.l.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef…
323 …%r = call <4 x float> @llvm.SI.gather4.c.b.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef…
336 …%r = call <4 x float> @llvm.SI.gather4.c.b.cl.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> un…
377 …%r = call <4 x float> @llvm.SI.gather4.c.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef…
[all …]
Dctpop.ll7 declare <8 x i32> @llvm.ctpop.v8i32(<8 x i32>) nounwind readnone
115 %ctpop = call <8 x i32> @llvm.ctpop.v8i32(<8 x i32> %val) nounwind readnone
Dsi-sgpr-spill.ll262 …%244 = call <4 x float> @llvm.SI.sampled.v8i32(<8 x i32> %243, <32 x i8> %62, <16 x i8> %64, i32 2)
307 …%278 = call <4 x float> @llvm.SI.sampled.v8i32(<8 x i32> %277, <32 x i8> %66, <16 x i8> %68, i32 2)
327 …%298 = call <4 x float> @llvm.SI.sampled.v8i32(<8 x i32> %297, <32 x i8> %82, <16 x i8> %84, i32 2)
345 …%316 = call <4 x float> @llvm.SI.sampled.v8i32(<8 x i32> %315, <32 x i8> %78, <16 x i8> %80, i32 2)
375 …%346 = call <4 x float> @llvm.SI.sampled.v8i32(<8 x i32> %345, <32 x i8> %62, <16 x i8> %64, i32 2)
405 …%376 = call <4 x float> @llvm.SI.sampled.v8i32(<8 x i32> %375, <32 x i8> %70, <16 x i8> %72, i32 2)
459 …%430 = call <4 x float> @llvm.SI.sampled.v8i32(<8 x i32> %429, <32 x i8> %86, <16 x i8> %88, i32 2)
601 …%572 = call <4 x float> @llvm.SI.sampled.v8i32(<8 x i32> %571, <32 x i8> %74, <16 x i8> %76, i32 2)
625 …%592 = call <4 x float> @llvm.SI.sampled.v8i32(<8 x i32> %591, <32 x i8> %62, <16 x i8> %64, i32 2)
664 declare <4 x float> @llvm.SI.sampled.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32) #1
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h81 v8i32 = 35, // 8 x i32 enumerator
220 SimpleTy == MVT::v8i32 || SimpleTy == MVT::v4i64); in is256BitVector()
290 case v8i32: in getVectorElementType()
330 case v8i32: in getVectorNumElements()
418 case v8i32: in getSizeInBits()
538 if (NumElements == 8) return MVT::v8i32; in getVectorVT()
DValueTypes.td58 def v8i32 : ValueType<256, 35>; // 8 x i32 vector value
/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp225 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost()
226 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost()
236 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, in getCastInstrCost()
256 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, in getCastInstrCost()
257 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, in getCastInstrCost()
405 { ISD::SELECT, MVT::v8i1, MVT::v8i32, 4*8 + 1*3 + 1*4 + 1*2 }, in getCmpSelInstrCost()
/external/llvm/lib/Target/R600/
DSIInstructions.td1748 defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v8i32>;
1871 def : SampleRawPattern<int_SI_gather4_b_cl, IMAGE_GATHER4_B_CL_V4_V8, v8i32>;
1877 def : SampleRawPattern<int_SI_gather4_c_cl, IMAGE_GATHER4_C_CL_V4_V8, v8i32>;
1879 def : SampleRawPattern<int_SI_gather4_c_l, IMAGE_GATHER4_C_L_V4_V8, v8i32>;
1881 def : SampleRawPattern<int_SI_gather4_c_b, IMAGE_GATHER4_C_B_V4_V8, v8i32>;
1882 def : SampleRawPattern<int_SI_gather4_c_b_cl, IMAGE_GATHER4_C_B_CL_V4_V8, v8i32>;
1887 def : SampleRawPattern<int_SI_gather4_cl_o, IMAGE_GATHER4_CL_O_V4_V8, v8i32>;
1889 def : SampleRawPattern<int_SI_gather4_l_o, IMAGE_GATHER4_L_O_V4_V8, v8i32>;
1891 def : SampleRawPattern<int_SI_gather4_b_o, IMAGE_GATHER4_B_O_V4_V8, v8i32>;
1892 def : SampleRawPattern<int_SI_gather4_b_cl_o, IMAGE_GATHER4_B_CL_O_V4_V8, v8i32>;
[all …]
DSIRegisterInfo.td173 def SReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 256, (add SGPR_256)>;
188 def VReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 256, (add VGPR_256)>;
DSIISelLowering.cpp49 addRegisterClass(MVT::v8i32, &AMDGPU::VReg_256RegClass); in SITargetLowering()
72 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand); in SITargetLowering()
86 setOperationAction(ISD::LOAD, MVT::v8i32, Custom); in SITargetLowering()
89 setOperationAction(ISD::STORE, MVT::v8i32, Custom); in SITargetLowering()
96 setOperationAction(ISD::LOAD, MVT::v8i32, Custom); in SITargetLowering()
163 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Expand); in SITargetLowering()
179 MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32 in SITargetLowering()
DAMDGPUISelLowering.cpp149 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32); in AMDGPUTargetLowering()
195 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32); in AMDGPUTargetLowering()
208 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom); in AMDGPUTargetLowering()
215 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom); in AMDGPUTargetLowering()
/external/llvm/test/CodeGen/X86/
Dbswap-vector.ll90 declare <8 x i32> @llvm.bswap.v8i32(<8 x i32>)
114 %r = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %v)
/external/llvm/lib/IR/
DValueTypes.cpp153 case MVT::v8i32: return "v8i32"; in getEVTString()
221 case MVT::v8i32: return VectorType::get(Type::getInt32Ty(Context), 8); in getTypeForEVT()
/external/llvm/lib/Target/X86/InstPrinter/
DX86InstComments.cpp106 DecodePSHUFMask(MVT::v8i32, in EmitAnyX86InstComments()
209 DecodeUNPCKHMask(MVT::v8i32, ShuffleMask); in EmitAnyX86InstComments()
282 DecodeUNPCKLMask(MVT::v8i32, ShuffleMask); in EmitAnyX86InstComments()
/external/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp452 { ISD::SELECT, MVT::v8i1, MVT::v8i32, 8 * AmortizationCost }, in getCmpSelInstrCost()
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
DSIISelLowering.cpp38 addRegisterClass(MVT::v8i32, &AMDGPU::SReg_256RegClass); in SITargetLowering()
/external/mesa3d/src/gallium/drivers/radeon/
DSIISelLowering.cpp38 addRegisterClass(MVT::v8i32, &AMDGPU::SReg_256RegClass); in SITargetLowering()
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp94 case MVT::v8i32: return "MVT::v8i32"; in getEnumName()
/external/llvm/test/Analysis/CostModel/X86/
Dvshift-cost.ll71 ; v16i16 and v8i32 shift left by non-uniform constant are lowered into
/external/llvm/include/llvm/IR/
DIntrinsics.td169 def llvm_v8i32_ty : LLVMType<v8i32>; // 8 x i32

12