| /external/llvm/include/llvm/CodeGen/ |
| D | MachineValueType.h | 86 v8i64 = 40, // 8 x i64 enumerator
227 SimpleTy == MVT::v8i64 || SimpleTy == MVT::v16i32); in is512BitVector()
295 case v8i64: in getVectorElementType()
331 case v8i64: in getVectorNumElements()
425 case v8i64: in getSizeInBits()
545 if (NumElements == 8) return MVT::v8i64; in getVectorVT()
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| D | ValueTypes.td | 63 def v8i64 : ValueType<512, 40>; // 8 x i64 vector value
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrAVX512.td | 6 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
8 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
11 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
12 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
14 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
16 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
94 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
160 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
177 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
[all …]
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| D | X86CallingConv.td | 55 CCIfType<[v16i32, v8i64, v16f32, v8f64],
109 CCIfType<[v16f32, v8f64, v16i32, v8i64],
255 CCIfNotVarArg<CCIfType<[v16i32, v8i64, v16f32, v8f64],
275 CCIfType<[v16i32, v8i64, v16f32, v8f64],
298 CCIfType<[v16i32, v16f32, v8f64, v8i64], CCPassIndirect<i64>>,
561 CCIfType<[v16f32, v8f64, v16i32, v8i64],
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| D | X86InstrFragmentsSIMD.td | 315 def loadv8i64 : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>;
391 (v8i64 (alignedload512 node:$ptr))>;
433 def memopv8i64 : PatFrag<(ops node:$ptr), (v8i64 (memop8 node:$ptr))>;
487 def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
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| D | X86TargetTransformInfo.cpp | 591 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 4 }, in getCastInstrCost()
619 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 9 }, in getCastInstrCost()
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| D | X86ISelLowering.cpp | 1331 addRegisterClass(MVT::v8i64, &X86::VR512RegClass); in resetOperationActions()
1346 setOperationAction(ISD::LOAD, MVT::v8i64, Legal); in resetOperationActions()
1394 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom); in resetOperationActions()
1396 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom); in resetOperationActions()
1402 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom); in resetOperationActions()
1411 setOperationAction(ISD::MUL, MVT::v8i64, Custom); in resetOperationActions()
1420 setOperationAction(ISD::SELECT, MVT::v8i64, Custom); in resetOperationActions()
1423 setOperationAction(ISD::ADD, MVT::v8i64, Legal); in resetOperationActions()
1426 setOperationAction(ISD::SUB, MVT::v8i64, Legal); in resetOperationActions()
1431 setOperationAction(ISD::SRL, MVT::v8i64, Custom); in resetOperationActions()
[all …]
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| D | X86RegisterInfo.td | 452 def VR512 : RegisterClass<"X86", [v16f32, v8f64, v16i32, v8i64], 512,
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| D | X86InstrCompiler.td | 834 (v8i64 (X86cmov VR512:$t, VR512:$f, imm:$cond,
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| /external/llvm/lib/Target/ARM/ |
| D | ARMTargetTransformInfo.cpp | 227 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, in getCastInstrCost()
228 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, in getCastInstrCost()
229 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, in getCastInstrCost()
230 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, in getCastInstrCost()
408 { ISD::SELECT, MVT::v8i1, MVT::v8i64, 50 }, in getCmpSelInstrCost()
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| D | ARMRegisterInfo.td | 387 def QQQQPR : RegisterClass<"ARM", [v8i64], 256, (add Tuples2QQ)> {
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| D | ARMISelDAGToDAG.cpp | 2019 SDValue RegSeq = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0); in SelectVST()
2140 SuperReg = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0); in SelectVLDSTLane()
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| D | ARMISelLowering.cpp | 924 case MVT::v8i64: in findRepresentativeClass()
1085 if (VT == MVT::v8i64) in getRegClassFor()
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| /external/llvm/lib/IR/ |
| D | ValueTypes.cpp | 158 case MVT::v8i64: return "v8i64"; in getEVTString()
226 case MVT::v8i64: return VectorType::get(Type::getInt64Ty(Context), 8); in getTypeForEVT()
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| /external/llvm/test/CodeGen/R600/ |
| D | ctpop64.ll | 6 declare <8 x i64> @llvm.ctpop.v8i64(<8 x i64>) nounwind readnone
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64TargetTransformInfo.cpp | 455 { ISD::SELECT, MVT::v8i1, MVT::v8i64, 8 * AmortizationCost }, in getCmpSelInstrCost()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenTarget.cpp | 99 case MVT::v8i64: return "MVT::v8i64"; in getEnumName()
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| /external/llvm/test/CodeGen/X86/ |
| D | avx512-intrinsics.ll | 371 %res = call <8 x i64> @llvm.ctlz.v8i64(<8 x i64> %a, i1 false)
375 declare <8 x i64> @llvm.ctlz.v8i64(<8 x i64>, i1) nounwind readonly
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| /external/llvm/include/llvm/IR/ |
| D | Intrinsics.td | 174 def llvm_v8i64_ty : LLVMType<v8i64>; // 8 x i64
|