1 // Copyright 2013, ARM Limited
2 // All rights reserved.
3 //
4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are met:
6 //
7 // * Redistributions of source code must retain the above copyright notice,
8 // this list of conditions and the following disclaimer.
9 // * Redistributions in binary form must reproduce the above copyright notice,
10 // this list of conditions and the following disclaimer in the documentation
11 // and/or other materials provided with the distribution.
12 // * Neither the name of ARM Limited nor the names of its contributors may be
13 // used to endorse or promote products derived from this software without
14 // specific prior written permission.
15 //
16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
27 #include "utils-vixl.h"
28 #include "a64/cpu-a64.h"
29
30 namespace vixl {
31
32 // Initialise to smallest possible cache size.
33 unsigned CPU::dcache_line_size_ = 1;
34 unsigned CPU::icache_line_size_ = 1;
35
36
37 // Currently computes I and D cache line size.
SetUp()38 void CPU::SetUp() {
39 uint32_t cache_type_register = GetCacheType();
40
41 // The cache type register holds information about the caches, including I
42 // D caches line size.
43 static const int kDCacheLineSizeShift = 16;
44 static const int kICacheLineSizeShift = 0;
45 static const uint32_t kDCacheLineSizeMask = 0xf << kDCacheLineSizeShift;
46 static const uint32_t kICacheLineSizeMask = 0xf << kICacheLineSizeShift;
47
48 // The cache type register holds the size of the I and D caches as a power of
49 // two.
50 uint32_t dcache_line_size_power_of_two =
51 (cache_type_register & kDCacheLineSizeMask) >> kDCacheLineSizeShift;
52 uint32_t icache_line_size_power_of_two =
53 (cache_type_register & kICacheLineSizeMask) >> kICacheLineSizeShift;
54
55 dcache_line_size_ = 1 << dcache_line_size_power_of_two;
56 icache_line_size_ = 1 << icache_line_size_power_of_two;
57 }
58
59
GetCacheType()60 uint32_t CPU::GetCacheType() {
61 #ifdef USE_SIMULATOR
62 // This will lead to a cache with 1 byte long lines, which is fine since the
63 // simulator will not need this information.
64 return 0;
65 #else
66 uint32_t cache_type_register;
67 // Copy the content of the cache type register to a core register.
68 __asm__ __volatile__ ("mrs %[ctr], ctr_el0" // NOLINT
69 : [ctr] "=r" (cache_type_register));
70 return cache_type_register;
71 #endif
72 }
73
74
EnsureIAndDCacheCoherency(void * address,size_t length)75 void CPU::EnsureIAndDCacheCoherency(void *address, size_t length) {
76 #ifdef USE_SIMULATOR
77 USE(address);
78 USE(length);
79 // TODO: consider adding cache simulation to ensure every address run has been
80 // synchronised.
81 #else
82 // The code below assumes user space cache operations are allowed.
83
84 uintptr_t start = reinterpret_cast<uintptr_t>(address);
85 // Sizes will be used to generate a mask big enough to cover a pointer.
86 uintptr_t dsize = static_cast<uintptr_t>(dcache_line_size_);
87 uintptr_t isize = static_cast<uintptr_t>(icache_line_size_);
88 // Cache line sizes are always a power of 2.
89 VIXL_ASSERT(CountSetBits(dsize, 64) == 1);
90 VIXL_ASSERT(CountSetBits(isize, 64) == 1);
91 uintptr_t dstart = start & ~(dsize - 1);
92 uintptr_t istart = start & ~(isize - 1);
93 uintptr_t end = start + length;
94
95 __asm__ __volatile__ ( // NOLINT
96 // Clean every line of the D cache containing the target data.
97 "0: \n\t"
98 // dc : Data Cache maintenance
99 // c : Clean
100 // va : by (Virtual) Address
101 // u : to the point of Unification
102 // The point of unification for a processor is the point by which the
103 // instruction and data caches are guaranteed to see the same copy of a
104 // memory location. See ARM DDI 0406B page B2-12 for more information.
105 "dc cvau, %[dline] \n\t"
106 "add %[dline], %[dline], %[dsize] \n\t"
107 "cmp %[dline], %[end] \n\t"
108 "b.lt 0b \n\t"
109 // Barrier to make sure the effect of the code above is visible to the rest
110 // of the world.
111 // dsb : Data Synchronisation Barrier
112 // ish : Inner SHareable domain
113 // The point of unification for an Inner Shareable shareability domain is
114 // the point by which the instruction and data caches of all the processors
115 // in that Inner Shareable shareability domain are guaranteed to see the
116 // same copy of a memory location. See ARM DDI 0406B page B2-12 for more
117 // information.
118 "dsb ish \n\t"
119 // Invalidate every line of the I cache containing the target data.
120 "1: \n\t"
121 // ic : instruction cache maintenance
122 // i : invalidate
123 // va : by address
124 // u : to the point of unification
125 "ic ivau, %[iline] \n\t"
126 "add %[iline], %[iline], %[isize] \n\t"
127 "cmp %[iline], %[end] \n\t"
128 "b.lt 1b \n\t"
129 // Barrier to make sure the effect of the code above is visible to the rest
130 // of the world.
131 "dsb ish \n\t"
132 // Barrier to ensure any prefetching which happened before this code is
133 // discarded.
134 // isb : Instruction Synchronisation Barrier
135 "isb \n\t"
136 : [dline] "+r" (dstart),
137 [iline] "+r" (istart)
138 : [dsize] "r" (dsize),
139 [isize] "r" (isize),
140 [end] "r" (end)
141 // This code does not write to memory but without the dependency gcc might
142 // move this code before the code is generated.
143 : "cc", "memory"
144 ); // NOLINT
145 #endif
146 }
147
148 } // namespace vixl
149